Masked Write Memory ECC Error Correction
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Solution Overview
Problem
Current semiconductor memory devices face challenges in securely performing masked write operations due to increasing defective memory cells and bit error rates, which affect data integrity, especially as manufacturing processes scale down.
Innovation Solution
The implementation of a method in memory devices that includes generating internal read and write commands to perform error detection and correction using an ECC engine, allowing for secure masked write operations by reading, modifying, and writing data while maintaining data integrity through error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If masked write operation is performed without error correction, then write operation speed is improved, but data integrity deteriorates due to increasing bit error rates
Solution Approach 1:
The patent performs error detection and correction operations before the actual write operation to memory cells. The ECC circuit reads previous data from memory cells, calculates parity bits, and prepares corrected data in advance, then performs the write operation. This preliminary action ensures data integrity is maintained while allowing high-speed masked write operations to proceed.
Solution Approach 2:
The patent implements a feedback mechanism where the ECC circuit continuously monitors data integrity by reading previous data from memory cells, comparing it with new data, and performing error correction. This feedback loop ensures that any bit errors detected during the masked write operation are immediately corrected, maintaining data integrity without slowing down the write process.
2Reliability
If error correction operations are performed during masked write operation, then data integrity is improved, but operation time increases
Solution Approach 1:
The patent performs error detection and correction operations before the actual write operation to memory cells. The ECC circuit reads previous data from memory cells, calculates parity bits, and prepares corrected data in advance, then performs the write operation. This preliminary action ensures data integrity is maintained while allowing high-speed masked write operations to proceed.
Solution Approach 2:
The patent maintains continuous operation by overlapping the error correction process with the masked write operation. The ECC circuit performs error detection and correction in parallel with the data writing process, ensuring that both operations occur simultaneously without increasing the overall operation time. This continuous action allows high-speed masked write operations to proceed while maintaining data integrity.
3Speed
If masked write operation is performed without reading previous data, then write operation speed is improved, but error detection capability deteriorates
Solution Approach 1:
The patent performs error detection and correction operations before the actual write operation to memory cells. The ECC circuit reads previous data from memory cells, calculates parity bits, and prepares corrected data in advance, then performs the write operation. This preliminary action ensures data integrity is maintained while allowing high-speed masked write operations to proceed.
Solution Approach 2:
The patent implements a feedback mechanism where the ECC circuit continuously monitors data integrity by reading previous data from memory cells, comparing it with new data, and performing error correction. This feedback loop ensures that any bit errors detected during the masked write operation are immediately corrected, maintaining data integrity without slowing down the write process.
Data Source
AI summary
A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.