Masking Pattern Formation for Integrated Circuit Pitch Reduction

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Solution Overview

Problem

The continuous reduction in feature sizes of integrated circuits poses challenges for conventional photolithographic techniques, which have a minimum pitch limit, making it difficult to form features with small pitches and high density, especially for non-linear shapes and varying sizes.

Innovation Solution

The method involves forming mandrels with a first pattern, depositing a second masking layer to bury the pattern, and creating sacrificial structures to define a second pattern with a smaller pitch, using anti-spacers to reduce the pitch further, allowing for the formation of features with various shapes and sizes in a target layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional photolithographic techniques are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to minimum pitch limits

Engineering Contradiction:
Improvefeature sizeVSAvoidpatterning process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the patterning process into multiple stages: forming mandrels with a first pitch, depositing spacer material, selectively removing portions, and repeating the process. This multi-stage segmentation enables achieving sub-photolithographic pitch features while managing process complexity through systematic breakdown of the fabrication sequence

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs preliminary actions by pre-forming mandrels that serve as templates for subsequent spacer formation. The mandrels are prepared in advance with specific patterns and dimensions that guide the final feature geometry, enabling precise pitch control before the actual feature formation occurs

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If pitch multiplication methods are used, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvepitch controlVSAvoidnumber of process steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent implements periodic action by repeating the cycle of depositing spacer material, selectively removing portions, and forming new mandrels multiple times. Each iteration of this periodic process multiplies the pitch further, enabling progressive refinement from initial mandrel pitch to final sub-photolithographic feature pitch through systematic repetition

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent transitions from two-dimensional planar patterning to three-dimensional spacer formation, utilizing vertical deposition and selective lateral removal. This dimensional change enables pitch multiplication by creating features in the vertical dimension that translate to precise horizontal pitch control, adding a new degree of freedom to the patterning process

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If feature density is increased, then productivity is improved, but manufacturing precision deteriorates due to difficulty in forming small pitch features

Engineering Contradiction:
Improvefeature densityVSAvoidsmall pitch formation
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent employs self-service mechanisms where spacer material automatically conforms to mandrel sidewalls through conformal deposition, and selective removal processes automatically define precise feature boundaries based on spacer thickness. This self-aligned approach eliminates the need for additional alignment steps, enabling high feature density while maintaining manufacturing precision through self-correcting process mechanics

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8871646B2Methods of forming a masking pattern for integrated circuits
Publication Date: 2014.10.28 MICRON TECHNOLOGY INC
  • US8871646B2 patent drawing
  • US8871646B2 patent drawing
  • US8871646B2 patent drawing

AI summary

In some embodiments, methods for forming a masking pattern for an integrated circuit are disclosed. In one embodiment, mandrels defining a first pattern are formed in a first masking layer over a target layer. A second masking layer is deposited to at least partially fill spaces of the first pattern. Sacrificial structures are formed between the mandrels and the second masking layer. After depositing the second masking layer and forming the sacrificial structures, the sacrificial structures are removed to define gaps between the mandrels and the second masking layer, thereby defining a second pattern. The second pattern includes at least parts of the mandrels and intervening mask features alternating with the mandrels. The second pattern may be transferred into the target layer. In some embodiments, the method allows the formation of features having a high density and a small pitch while also allowing the formation of features having various shapes and sizes.