Masking Pattern Selection for IC Fault Isolation
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Solution Overview
Problem
Digital Integrated Circuits (ICs) face defects during manufacturing that current testing techniques struggle to accurately identify, as they often provide inadequate information about failing logic elements, leading to inefficiencies in chip quality and production costs.
Innovation Solution
A method and system that apply a test vector to semiconductor chips, using masking patterns to isolate and compare results, determining failure rates, and employing various sweep methods (single-level, double-level, triple-level, and recursive binary sweeps) to identify faulty logic elements, optimizing the testing process by selectively masking and activating scan channels to isolate faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional testing techniques are used to test digital ICs, then testing can be performed, but the ability to accurately identify and isolate faulty logic elements is insufficient
Solution Approach 1:
The patent applies segmentation by dividing the scan channels into multiple segments and using masking patterns to isolate and test specific segments independently. This allows precise identification of faulty logic elements by testing individual segments rather than the entire circuit at once, thereby improving fault isolation precision while maintaining adequate information about fault locations.
Solution Approach 2:
The patent introduces masking patterns as an intermediary mechanism between the test vector and the logic elements. These masking patterns selectively enable or disable specific scan channels, acting as a mediator that controls which portions of the circuit are tested. This intermediary approach enhances fault isolation precision without losing information about which specific elements are faulty.
2Reliability
If comprehensive testing of all logic elements is performed, then complete fault coverage is achieved, but testing time and cost increase
Solution Approach 1:
The patent applies partial action by using masking patterns to test only specific segments of scan channels rather than all logic elements simultaneously. The system dynamically determines which segments require testing based on failure rates and fault probability, achieving sufficient fault detection coverage while reducing unnecessary testing of already-verified segments, thereby decreasing testing time.
Solution Approach 2:
The patent implements periodic action through iterative testing cycles where masking patterns are adjusted based on results from previous test iterations. The system periodically re-tests segments with higher failure rates while reducing or eliminating testing of segments with acceptable failure rates, maintaining reliable fault detection coverage while optimizing testing time through adaptive re-testing.
Data Source
AI summary
A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference.