Maskless Air Gap via Single Damascene Process

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Solution Overview

Problem

Conventional techniques for reducing capacitive coupling between metal lines in integrated circuits, such as forming air gaps, face challenges with unlanded vias causing shorts and require complex masking processes that do not scale with decreasing pitch, leading to increased manufacturing costs and reduced yield.

Innovation Solution

A maskless air gap process using a single damascene technique, where vias are patterned and metallized before the air gap etch, eliminating the need for masked layers and allowing all parts of the structure to benefit from the air gap, thereby reducing capacitance and manufacturing complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional masking techniques are used to prevent unlanded via punching through air gap, then shorts are prevented, but manufacturing complexity and cost increase significantly

Engineering Contradiction:
Improveprevention of shortsVSAvoidmasking process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The via is formed before the air gap etch process, so that when the air gap is created, the via already exists as a landed structure. This preliminary formation of the via eliminates the need for subsequent masking to prevent punching through, as the via cannot punch through an already-formed structure.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The conventional sequence is inverted: instead of forming air gap first then protecting it with masks, the via is formed first and then the air gap is formed around it. This inversion of the process sequence naturally prevents the punching through issue without requiring masks.

Inventive Principle:
Principle #13The other way round (Inversion)

2Manufacturing precision

If multiple lithography masks are used to mask off vias locally, then air gap etching is controlled, but manufacturing cost and process time increase

Engineering Contradiction:
Improveair gap etching controlVSAvoidmanufacturing efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The via structure is preliminarily formed before the air gap etch, providing a natural etch stop that controls where the air gap forms. This eliminates the need for additional lithography masks to control the etching boundaries, streamlining the manufacturing process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The via structure itself serves as the boundary definition for the air gap etch. The etch process naturally stops at the via structure without requiring external masking, making the via structure self-sufficient for controlling the air gap formation.

Inventive Principle:
Principle #25Self-service

3Use of energy by moving object

If air gap is formed before via landing, then capacitance reduction is achieved, but unlanded via causes shorts

Engineering Contradiction:
Improvecapacitance reductionVSAvoidvia landing reliability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The via is formed in advance before the air gap etch process. This ensures that when the air gap is created around the via, the via already has its final landed position and structure, preventing any shorting while still allowing the air gap to form for capacitance reduction.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The via structure is formed beforehand to serve as a protective cushion that prevents the air gap etch from creating shorts. The via acts as a pre-positioned barrier that ensures proper landing while allowing the air gap to form in the surrounding areas.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11610810B2Maskless air gap enabled by a single damascene process
Publication Date: 2023.03.21 INTEL CORP
  • US11610810B2 patent drawing
  • US11610810B2 patent drawing
  • US11610810B2 patent drawing

AI summary

A method for fabricating an integrated circuit comprises forming one or more conductive features supported by pillars of a first insulating layer in a first metal layer. One or more vias are formed in a via layer, the one or more vias over and on the first metal layer and in electrical connection with ones of the one or more conductive features. Subsequent to via formation, air gaps are between adjacent ones of the one or more conductive features in the first metal layer to separate the one or more conductive features. A second insulating layer is formed over the one or more conductive features and over the one or more vias, such that the second insulating layer covers the first metal layer and the via layer while bridging over the air gaps, wherein tops the air gaps are substantially coplanar with tops of the one or more conductive features.