Maskless Self-Aligned Contact Process for FinFET Fabrication
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Solution Overview
Problem
Conventional semiconductor fabrication processes are complex and costly due to the need for multiple masking steps, which increases manufacturing complexity and reduces device yield, even in maskless self-aligned processes.
Innovation Solution
A maskless contact process is used that is self-aligned to both the gate and active area, eliminating the need for certain masking steps and improving device density, allowing for the efficient manufacture of devices like FINFETs and trigate structures by exposing underlying epitaxial layers and depositing metal material in contact with source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple masking steps are used in conventional semiconductor fabrication, then transistor and device structures can be manufactured, but manufacturing complexity and costs increase significantly
Solution Approach 1:
The patent extracts and eliminates the masking step from the conventional fabrication process by implementing a maskless self-aligned contact formation method. The contact holes are formed directly through the dielectric layer using plasma etching with self-alignment to the gate structure, removing the need for separate photolithographic masking steps while maintaining manufacturing capability
Solution Approach 2:
The gate structure serves as a self-aligning reference for contact hole formation. The plasma etching process uses the gate structure itself as the alignment reference, allowing contact holes to be automatically positioned correctly without external masks. This self-service mechanism eliminates the need for separate masking operations
2Device complexity
If maskless self-aligned processes are used to reduce masking steps, then some complexity is reduced, but significant density loss occurs which impacts device yield
Solution Approach 1:
The patent modifies the plasma etching parameters to achieve anisotropic etching with high vertical selectivity. By adjusting gas flow rates, power, and pressure parameters, the process achieves precise depth control and vertical sidewalls, preventing lateral etching that would cause density loss while maintaining the maskless self-aligned approach
3Manufacturing precision
If multiple masking steps are implemented, then device structures can be formed with proper alignment, but manufacturing time and costs increase
Solution Approach 1:
The patent merges the contact hole formation step with the existing plasma processing capability, eliminating the need for separate photolithography and etching steps. The single plasma etching process simultaneously achieves both the contact hole formation and self-alignment to the gate, reducing the number of discrete manufacturing steps while maintaining precision
Solution Approach 2:
The dielectric layer is pre-formed and planarized before contact hole formation, creating a ready-to-etch surface with proper topology. This preliminary preparation ensures that the subsequent plasma etching can proceed directly with self-alignment without requiring additional masking or alignment steps, reducing overall manufacturing time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, improves device density, and simplifies the semiconductor fabrication process by eliminating the need for multiple masking steps, while maintaining high yield and efficiency.
Implementation Method 1
removing dielectric material adjacent to the at least one gate structure using a maskless process
Implementation Method 2
depositing metal material on the exposed underlying epitaxial layer to form contact metal
Data Source
AI summary
Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming at least one gate structure over a plurality of fin structures. The method further includes removing dielectric material adjacent to the at least one gate structure using a maskless process, thereby exposing an underlying epitaxial layer formed adjacent to the at least one gate structure. The method further includes depositing metal material on the exposed underlying epitaxial layer to form contact metal in electrical contact with source and drain regions, adjacent to the at least one gate structure. The method further includes forming active areas and device isolation after the formation of the contact metal, including the at least one gate structure. The active areas and the contact metal are self-aligned with each other in a direction parallel to the at least one gate structure.