Maskless Frame Reveals for Aligning Opaque IC Interconnect Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing density of interconnects in integrated circuits (ICs) leads to challenges in filling high-aspect-ratio via openings and trenches with conductive material, and the featureless, planarized interconnect material layers pose difficulties in lithographic patterning due to opacity issues, making it hard to align lithographic features with underlying IC structures.
Innovation Solution
A method for subtractive patterning of opaque material layers using a maskless reveal of key areas, employing digital light processing (DLP) lithography and photoresist direct writing to expose regions around alignment features, allowing for initial alignment and subsequent etching to render underlying features visible for precise alignment, followed by nanometer-resolution patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If interconnect material layers are deposited upon highly planarized surfaces to achieve uniform thickness, then manufacturing precision is improved, but the featureless planarized surface makes it difficult to align lithographic features with underlying IC structures
Solution Approach 1:
Alignment marks are formed in the interconnect material layer before the main lithographic patterning step. These marks are created by selectively removing material at predetermined locations to expose underlying features, establishing reference points that guide subsequent alignment operations.
Solution Approach 2:
The alignment marks serve as an intermediary element between the lithographic system and the underlying IC structures. They provide visible reference features that the lithographic system can detect and use for precise alignment, bridging the gap created by the featureless planarized surface.
2Manufacturing precision
If subtractive patterning is used to pattern interconnect features, then the ability to create fine features is improved, but the opaque interconnect material layer prevents lithographic alignment systems from locating underlying alignment marks
Solution Approach 1:
The interconnect material layer is selectively removed at specific locations to create openings that expose underlying alignment marks. This segmentation allows the alignment marks to be visible and accessible for lithographic alignment while the rest of the opaque material layer remains intact for subsequent patterning operations.
Solution Approach 2:
The interconnect material layer has different properties at different locations: it is removed at alignment mark locations to provide visibility and transparency for alignment, while remaining intact in other areas to maintain the opaque, featureless surface required for precise subtractive patterning.
3Productivity
If via openings and trenches are etched with high aspect ratios to accommodate greater device density, then transistor density is improved, but the difficulty of filling these features with conductive material increases
Solution Approach 1:
Instead of filling the via openings and trenches with conductive material as in conventional approaches, the patent inverts the process by depositing an opaque interconnect material layer over the planarized surface and then selectively removing it to expose underlying features. This inversion eliminates the need to fill high-aspect-ratio features while achieving the same electrical connectivity function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise alignment and patterning of interconnect features within ICs, overcoming the opacity challenges and achieving nanometer resolution in IC fabrication, even with opaque material layers, thereby improving the density and performance of IC interconnects.
Implementation Method 1
employing digital light processing (DLP) lithography and photoresist direct writing to expose regions around alignment features
Implementation Method 2
photoresist direct writing to expose regions around alignment features
Data Source
Figure 1
Figure 2A~2B
Figure 2C~2D
AI summary
Integrated circuitry comprising an opaque material layer, such an interconnect metallization layer is first patterned with a maskless lithography to reveal an alignment feature, and is then patterned with masked lithography that aligns to the alignment feature. In some examples, the maskless lithography employs an I-line digital light processing (DLP) lithography system. In some examples the I-line DLP lithography system performs an alignment with IR illumination through a backside of a wafer. The maskless pattern may include dimensionally large windows within a frame around circuitry regions. A first etch of the opaque material layer may expose the alignment feature within the window, and a second etch of the opaque material may form IC features, such as interconnect metallization features.