Massbit Counter Sampling Rate Adjustment for Memory Verification
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in accurately measuring the threshold voltage distribution shape and characteristics of memory cells, which affects the precision of program and read operations.
Innovation Solution
A memory device with a massbit counter that adjusts the sampling rate and scaling ratio based on off-cell counting results during program loops to improve the accuracy of off-cell counting operations, allowing for both rough and precise counting as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fixed sampling rate is used for off-cell counting operations, then the device complexity is reduced, but the measurement precision of threshold voltage distribution cannot be adjusted based on specific memory operations
Solution Approach 1:
The patent implements a dynamic sampling rate adjustment mechanism where the sampling rate is no longer fixed but adapts based on the specific memory operation being performed. The controller selectively changes the sampling rate between a first sampling rate for rough counting and a second sampling rate for precise counting, allowing the system to optimize measurement precision for different operations (program, read, verify) while managing device complexity through controlled adaptability.
Solution Approach 2:
The patent changes the sampling rate parameter dynamically based on the type of memory operation. Different sampling rates are applied depending on whether the operation is program, read, or verify, allowing the system to achieve high measurement precision when needed while maintaining operational efficiency. This parameter change approach enables flexible adjustment of counting accuracy without requiring complete system redesign.
2Measurement precision
If a high sampling rate is used for all off-cell counting operations, then the measurement precision is improved, but the productivity of memory operations is reduced
Solution Approach 1:
The patent applies partial precision by using different sampling rates for different operations. Instead of always using the highest sampling rate (excessive precision), the system uses a first sampling rate for operations where rough counting suffices and a second, higher sampling rate only when precise counting is required. This selective application of precision maintains productivity while achieving necessary measurement accuracy for each specific operation type.
Solution Approach 2:
The dynamic adjustment of sampling rate allows the system to optimize the balance between precision and productivity in real-time. The controller selectively changes the sampling rate based on the current memory operation, ensuring that high precision is applied only when necessary rather than continuously, thus maintaining overall system productivity while achieving required measurement accuracy.
3Adaptability or versatility
If the sampling rate is adjusted based on off-cell counting results, then the adaptability of the memory device is improved, but the device complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the controller receives off-cell counting results and uses this information to selectively change the sampling rate for subsequent operations. The feedback loop allows the system to adapt to the actual state of the memory cells and adjust the counting precision accordingly, improving adaptability to different memory operations and conditions while managing complexity through purposeful feedback utilization.
Solution Approach 2:
The system dynamically adjusts the sampling rate based on feedback from off-cell counting results, enabling adaptability to different memory operations and cell states. This dynamic control allows the device to be versatile across different operations (program, read, verify) while the complexity is managed through structured control logic that responds to actual operational needs rather than requiring complex pre-programming for all scenarios.
Data Source
AI summary
A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.