Master Chip Dynamic Latency Control for Voltage-Dependent Speed
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Solution Overview
Problem
Integrated circuit chips face challenges in optimally setting latency due to changes in operation speeds caused by varying power supply voltage levels, which affects communication efficiency between chips.
Innovation Solution
A master chip detects changes in the operation speed of a slave chip and sets optimal latency by measuring and storing operation times at different power supply voltage levels, allowing for consistent latency control regardless of voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the power supply voltage level is changed to optimize operation speed, then the operation speed changes, but the latency setting becomes suboptimal
Solution Approach 1:
The patent implements dynamic latency adjustment by storing multiple latency values corresponding to different power supply voltage levels. When the power supply voltage changes, the system dynamically selects and applies the appropriate latency value from storage, ensuring optimal latency settings adapt to current operating conditions rather than using a fixed latency value
Solution Approach 2:
The patent changes the latency parameter based on power supply voltage levels. By storing latency values associated with specific voltage levels and selecting the appropriate latency value when voltage changes occur, the system adjusts the latency parameter to maintain optimality across different operating conditions
2Device complexity
If a fixed latency value is used for all power supply voltage levels, then the system configuration is simple, but communication efficiency deteriorates when voltage changes
Solution Approach 1:
The patent performs preliminary action by pre-storing multiple latency values corresponding to different power supply voltage levels before actual operation. When the power supply voltage changes, the system can immediately retrieve and apply the appropriate pre-stored latency value, avoiding communication efficiency degradation without requiring complex real-time calculations
Solution Approach 2:
The patent implements feedback by detecting changes in power supply voltage levels and responding by selecting the appropriate latency value from storage. This feedback mechanism ensures that latency settings automatically adapt to voltage changes, maintaining communication efficiency without requiring manual reconfiguration
Data Source
AI summary
A system includes a first chip configured to supply a training command and a second chip configured to transfer to the first chip a measured time for performing an operation in response to the training command.