Master Clock Synchronization for Phase-Aligned Clock Gating
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Solution Overview
Problem
Existing clock management circuits in portable electronic devices lose phase synchronization between multiple clocks when one or more clock signals are disabled and later enabled, leading to sub-optimal power management, reduced battery life, and increased heat dissipation.
Innovation Solution
A clock generator circuit that divides a reference clock signal by at least a factor of two to generate a master clock signal, synchronizing each phase circuit with the master clock signal's edge to maintain predetermined phase relationships between output clock signals, ensuring phase consistency during enablement and disablement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock signals are selectively disabled to save power, then power consumption is reduced, but phase synchronization between clocks is lost when re-enabled
Solution Approach 1:
A synchronization circuit acts as an intermediary between the clock enable signal and the phase circuit. This intermediary monitors the master clock signal and only enables the phase circuit during valid synchronization edges, ensuring phase alignment is maintained even after the clock was disabled for power saving.
Solution Approach 2:
The synchronization circuit provides feedback by monitoring the master clock signal and adjusting the enablement timing of the phase circuit accordingly. This feedback mechanism ensures that the phase circuit is only enabled when the master clock is in a valid state, maintaining phase synchronization.
2Adaptability or versatility
If multiple circuits are simultaneously active, then device functionality is complete, but current draw from battery increases
Solution Approach 1:
The system uses periodic clock signals with controlled duty cycles to activate different circuits at different times. By staggering the active periods of multiple circuits through phase control, the device maintains full functionality across different time periods while reducing peak current draw from the battery.
3Duration of action of moving object
If clock phase relationships are staggered to balance load, then battery life is extended, but device complexity increases
Solution Approach 1:
The synchronization circuit performs multiple functions: it monitors the master clock signal, determines valid synchronization edges, controls the enablement timing of phase circuits, and maintains phase alignment. This multi-functional approach achieves load balancing and battery life extension without proportionally increasing device complexity.
Data Source
AI summary
A clock generation circuit is operative to disable and enable a plurality of output clock signals while maintaining predetermined phase relationships between the clock signals. A reference clock signal is divided by a factor of at least two, to generate a master clock signal. A plurality of phase circuits, each independently enabled, generates a plurality of output clock signals by dividing the reference clock signal. The output clock signals have predetermined phase relationships relative to each other. Each phase circuit is enabled synchronously to a synchronization edge of the master clock signal. A synchronization circuit associated with each phase circuit ensures synchronization with the master clock signal by outputting a phase circuit enable signal only upon the conditions of a clock enable signal associated with the output clock being asserted and the receipt of a predetermined number of master clock signal synchronizing edges.