Master-Clone Optimization via Single Block Netlist
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Solution Overview
Problem
The optimization of large and complex integrated circuits (ICs) with master-clone scenarios is challenging due to inaccurate timing budgets and the complexity of synchronizing multiple instances of design IP, especially when using traditional methods and Reverse Interface Logic Model (ReverseILM), which leads to inefficient analysis and optimization.
Innovation Solution
A computer-implemented method that identifies a target block in an IC design, converts the external area into a macro with a physical and timing library, and represents it as a single block netlist for optimization, using donut macros and cloud libraries to simplify the analysis and optimization process, particularly effective for timing, performance, and power optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional timing budget approach is used for master-clone optimization, then the analysis process is simplified, but the timing information becomes inaccurate and static, degrading optimization quality
Solution Approach 1:
The patent segments the circuit analysis into two distinct phases: a global timing budget phase that provides initial timing information, and a local detailed analysis phase that refines timing accuracy for master-clone interfaces. This segmentation allows the system to maintain both computational efficiency and timing precision by applying different analysis depths to different parts of the circuit.
Solution Approach 2:
The patent performs preliminary global timing analysis to establish initial timing budgets before conducting detailed local analysis. This preliminary action provides a foundation that guides subsequent detailed optimization, ensuring both overall timing compliance and local interface accuracy without requiring full detailed analysis from the start.
2Measurement precision
If Reverse Interface Logic Model (ReverseILM) is used to account for accurate interface timing, then timing accuracy is improved, but external timing and physical context differ for each master-clone instance, leading to difficult iterative synchronization
Solution Approach 1:
The patent creates a universal interface model that can be applied to all master-clone instances. This single model captures the essential timing and physical context relationships, allowing it to be reused across multiple instances without requiring separate customized models for each, thereby reducing synchronization complexity while maintaining accuracy.
Solution Approach 2:
The patent uses copying by creating a standardized interface model that can be instantiated and applied to multiple master-clone pairs. Instead of developing unique models for each instance, the same validated interface model is copied and applied across all instances, ensuring consistency and simplifying synchronization while maintaining timing accuracy.
3Adaptability or versatility
If multiple instances of design IP are analyzed separately, then each instance can be optimized independently, but the overall computational complexity increases and optimization quality degrades
Solution Approach 1:
The patent merges the analysis of multiple master-clone instances by establishing their interrelationships through a unified timing model. Instead of treating instances as completely separate entities, the system combines their analysis by sharing common interface models and timing constraints, reducing redundant computations while preserving the ability to optimize each instance's specific characteristics.
Data Source
AI summary
A system, method and/or computer program for optimizing a circuit design. In some embodiments, a target block with an external boundary and external boundary pins is identified in an integrated circuit design. An area outside the target block is converted into a first macro, wherein the first macro has a physical library and a timing library and wherein the physical library has an internal boundary that corresponds to the external boundary of the target block and wherein the physical library has internal boundary pins that correspond to the external boundary pins of the target block. The target block is represented as a single block netlist and the block netlist is optimized with respect to the first macro. The steps may be repeated with respect to a master and clone(s) on the same integrated circuit enabling a single block netlist to be optimized for multiple instances of the same design IP.