Master Communication Circuit Asynchronous Data Transmission
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Solution Overview
Problem
In one-line communication modes for debugging integrated circuits, achieving accurate clock synchronization between master and slave communication circuits is challenging due to differences in main clock frequencies, making it difficult to reduce clock deviation and necessitate additional oscillators, which is impractical for debugging.
Innovation Solution
A master communication circuit with a timer circuit that detects different times for transmitting logical levels, allowing the slave communication circuit to receive data without precise clock synchronization, using a configuration that includes output circuits to manage signal levels and a holding circuit to maintain signal levels on the communication line, enabling data transmission and reception with reduced terminal count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If one-line communication mode is used to reduce terminals, then the number of terminals is reduced, but clock synchronization accuracy deteriorates
Solution Approach 1:
The master communication circuit performs preliminary actions by driving the communication line to specific signal levels (first signal level for data '1', second signal level for data '0') before the slave circuit needs to read the data. This preliminary signal preparation allows the slave circuit to read data at its own timing without requiring precise clock synchronization with the master circuit.
Solution Approach 2:
The communication line acts as an intermediary that carries signal levels between the master and slave circuits. The master circuit prepares signals on this intermediary line, and the slave circuit reads signals from it at its own timing, eliminating the need for direct clock synchronization between the two circuits.
2Measurement precision
If additional oscillators are added to improve clock accuracy, then clock synchronization accuracy is improved, but device complexity increases
Solution Approach 1:
The invention extracts the clock synchronization requirement from the communication system by using asynchronous read timing. The slave circuit reads data at its own timing without needing synchronized clocks, thereby removing the need for additional oscillators and clock synchronization mechanisms.
Solution Approach 2:
Each communication circuit operates independently at its own timing rhythm. The master circuit prepares signals and the slave circuit reads them at its own timing, making each circuit self-sufficient without requiring external clock synchronization or additional oscillators.
3Reliability
If clock deviation is reduced to ensure accurate data transmission, then data transmission reliability is improved, but manufacturing difficulty increases
Solution Approach 1:
The master communication circuit prepares data signals in advance by driving the communication line to appropriate levels before the slave circuit needs to read them. This preliminary preparation ensures reliable data transmission without requiring the slave circuit to read at precisely synchronized timing, thereby reducing manufacturing difficulty.
Solution Approach 2:
The invention changes the timing parameter relationship between master and slave circuits from synchronized to asynchronous. The slave circuit reads data at its own timing regardless of master circuit timing, which maintains transmission reliability while significantly easing manufacturing requirements for clock synchronization.
Data Source
AI summary
A master communication circuit communicatively connected to a slave communication circuit, comprises a timer circuit that can detect a first time; a first output circuit that outputs a first output signal of one logical level for starting a detecting operation of the first time in the timer circuit, when a value transmitted to the slave communication circuit is one logical level, and for starting a detecting operation of a second time longer than the first time in the slave communication circuit; and a second output circuit that outputs a second output signal of the other logical level when the timer circuit detects the first time, wherein if a value of one logical level is transmitted to the slave communication circuit, the value of one logical level is transmitted to the slave communication circuit by not detecting the second time with the slave communication circuit, detecting the first time with the timer circuit, and outputting the second output signal with the second output circuit, and wherein if a value of the other logical level is transmitted to the slave communication circuit, the value of the other logical level is transmitted to the slave communication circuit by not detecting the first time with the timer circuit and detecting the second time with the slave communication circuit.