Master Device Dirty Bit Analysis Bus Traffic Reduction

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Solution Overview

Problem

In current SoC design, data transmission efficiency is limited as all data segments are transmitted over the bus, even if only some segments need updating, leading to increased bus traffic and reduced development speed.

Innovation Solution

A master device with a finite state machine (FSM) and multiplexers that analyze dirty bits to selectively transmit only the necessary data segments and their location information over the bus, reducing unnecessary data transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If all data segments are transmitted over the bus, then complete data is delivered to the slave, but bus traffic increases and transmission efficiency decreases

Engineering Contradiction:

Improvedata transmission efficiencyVSAvoidbus traffic

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent divides data into multiple segments and transmits only the dirty (modified) segments rather than the entire data set. The master device identifies which segments have changed using dirty bits and selectively transmits only those segments over the bus, reducing the quantity of data transmitted while maintaining data integrity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent extracts and transmits only the necessary portion of data (dirty segments) rather than the complete data set. By identifying segments with dirty bits set to logic 1, the system extracts only the modified segments for transmission, eliminating unnecessary data transfer and reducing bus traffic.

Inventive Principle:

Principle #2Taking out (Extraction)

2Quantity of substance

If selective transmission of dirty segments is implemented, then bus traffic is reduced, but device complexity increases due to FSM and multiplexers

Engineering Contradiction:

Improvebus trafficVSAvoidmaster device complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent introduces dynamic control mechanisms including a finite state machine (FSM) that adapts its behavior based on the state of dirty bits. The FSM dynamically determines which segments to transmit by analyzing dirty bit patterns, and multiplexers dynamically select and route only the necessary dirty segments to the bus, providing flexible and efficient data transmission.

Inventive Principle:

Principle #15Dynamics

3Productivity

If dirty bits are analyzed and processed, then only updated segments are transmitted, but processing time and complexity increase

Engineering Contradiction:

Improvetransmission efficiencyVSAvoiddata processing time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent performs preliminary analysis of dirty bits before data transmission. The master device examines the dirty bit status of each segment in advance, identifies which segments require transmission, and prepares the selective transmission list before actually sending data over the bus. This preliminary action prevents unnecessary transmission decisions during the actual data transfer process.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10108568B2Master capable of communicating with slave and system including the master

Publication Date: 2018.10.23 SAMSUNG ELECTRONICS CO LTD

AI summary

A master for transmitting data to a slave via a bus segment by segment is provided. The master includes a finite state machine (FSM) configured to receive and analyze dirty bits for first data segments to be included in a current segment among the data and to output a first selection signal and location information related to the current segment according to an analysis result and a first multiplexer configured to determine whether to output the current segment as a dirty data segment to the bus based on the first selection signal.