Master Memory Controller for Two-Dimensional Memory Bandwidth
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Solution Overview
Problem
High latency and variable latency memory modules in main memory systems lead to significant data bandwidth loss due to idle time in memory channels, which existing technologies fail to efficiently address.
Innovation Solution
The implementation of a two-dimensional memory array with a master memory controller that aggregates multiple random memory accesses into compound requests, allowing concurrent access to multiple memory slices across different memory modules within the same memory channel, thereby reducing idle time and enhancing data bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory modules with higher latency or variable latency are introduced into the main memory, then memory capacity and flexibility are improved, but data bandwidth loss becomes more significant due to idle time in memory channels
Solution Approach 1:
The memory channel operations are segmented into multiple independent transactions that can be pipelined. Instead of waiting for each memory transaction to complete sequentially, the system divides the memory access into stages and overlaps multiple transactions in the memory channel, allowing continuous data flow even when individual transactions have variable latency
Solution Approach 2:
The system performs preliminary actions by pre-fetching data and preparing memory transactions before they are actually needed. The memory controller anticipates future memory access patterns and initiates transactions in advance, so that data is ready when needed, reducing idle time in the memory channel
2Ease of operation
If conventional single-address memory transactions are used, then memory access simplicity is maintained, but data bandwidth is reduced due to idle time waiting for the next address
Solution Approach 1:
Multiple single-address memory transactions are merged into a single compound memory transaction that accesses multiple addresses simultaneously. The memory controller combines several individual memory access requests into one aggregated transaction, allowing the memory channel to transfer multiple data elements in parallel, thereby eliminating idle time between address transitions while maintaining simple programming interfaces
Solution Approach 2:
The memory system maintains continuous useful action by ensuring that the memory channel is always engaged in productive data transfer. Through transaction aggregation and pipelining, the system eliminates idle cycles between memory operations, keeping the data bus continuously utilized with meaningful data flow, thus maximizing bandwidth without complicating the access model
Data Source
AI summary
In one embodiment of the invention, a method of upgrading main memory in a computer system is disclosed. The method includes plugging a plurality of two dimensional memory modules into a plurality of memory module sockets and coupling a master memory controller between one or more processors and the plurality of memory modules. Each of the two dimensional memory modules includes memory in a plurality of memory slices and a plurality of slave memory controllers respectively coupled to the memory in the plurality of memory slices. According, the upgrading method further includes buffering and transposing data between a column by column format for the one or more processors and a row by row format for the memory in the plurality of memory slices.