Master Security Check Register for Secure Access State Awareness

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Solution Overview

Problem

Existing security mechanisms in processing systems are inadequate as they often require significant processing overhead to handle errors when a master attempts to access secure resources while in a non-secure state, as the master is typically unaware of its operating state and may incorrectly attempt to access secure resources.

Innovation Solution

A security mechanism that includes a master security check register allowing masters to check their operating state before accessing resources, eliminating the need for error signals and associated processing overhead by returning a data value indicating the current security state, thus enabling secure or non-secure access accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a master attempts to access secure resources without knowing its security state, then the master may successfully access resources it should not access, but the security mechanism must block such attempts and generate error signals, increasing processing overhead

Engineering Contradiction:
Improvesecurity state awarenessVSAvoidprocessing overhead
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by enabling masters to check their security state before attempting to access secure resources. The master security check register allows a master to query its current security state in advance, so it can determine whether it is authorized to access secure resources before making the actual access attempt. This prevents unauthorized access attempts and eliminates the need for error handling overhead.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the security mechanism blocks unauthorized access attempts and generates error signals, then security is maintained, but the master must take additional actions to resolve errors, increasing system complexity and processing time

Engineering Contradiction:
Improvesecurity enforcementVSAvoiderror handling mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies self-service by enabling the master to autonomously determine its security state through the master security check register without requiring external security management intervention. The master can independently query its security state and make informed decisions about resource access, eliminating the need for complex error signaling and resolution mechanisms between security management and the master.

Inventive Principle:
Principle #25Self-service

3Ease of operation

If the master is unaware of its operating state, then the master can operate independently, but it cannot make informed decisions about resource access, reducing system efficiency

Engineering Contradiction:
Improvemaster independenceVSAvoidresource access efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent applies feedback by providing the master with information about its current security state through the master security check register. When the master queries the register, it receives feedback about its authorized access level, enabling it to make informed decisions about whether to attempt access to secure resources. This feedback mechanism maintains master independence while significantly improving resource access efficiency.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9268970B2System and method for security-aware master
Publication Date: 2016.02.23 ANALOG DEVICES INC
  • US9268970B2 patent drawing
  • US9268970B2 patent drawing
  • US9268970B2 patent drawing

AI summary

A security-aware master is provided, such that a master can determine its security state before attempting access to secure resources or before requesting secure access level. An exemplary system include a system interconnect; one or more masters coupled with the system interconnect; and a master security check register coupled with the system interconnect. The master security check register is configured to receive a request from a master via the system interconnect to access the master security check register, wherein the request includes a master operating state signal that indicates a security state of the master requesting access, and return a data value to the master based on the master operating state signal, wherein the data value indicates a current security state of the master requesting access.