Master-Slave Chip Link Without Slave PLL
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Solution Overview
Problem
Existing chip-to-chip communication protocols, such as PCI, are over-engineered and consume excessive power and space, leading to electromagnetic interference (EMI) issues and inefficiencies in adapting to changing technologies, particularly at higher clock speeds.
Innovation Solution
A chip-to-chip communication system where a master IC with a PLL generates a clock signal, and a slave IC without a PLL or clock, allowing for flexible frequency changes and reduced power consumption, mitigating EMI by eliminating the need for a slave PLL and enabling quick frequency adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a slave PLL is included in the slave device, then clock synchronization is maintained, but power consumption increases
Solution Approach 1:
The patent removes the PLL from the slave device, extracting the clock generation function from the slave side. The master device generates the clock signal and transmits it to the slave device, eliminating the need for a slave PLL and its associated power consumption while maintaining clock synchronization through the transmitted clock signal.
2Adaptability or versatility
If the master clock changes frequency quickly, then adaptability to changing technologies improves, but electromagnetic interference increases
Solution Approach 1:
The patent implements dynamic frequency adjustment by allowing the master clock to change frequency quickly in response to changing technological requirements. The system dynamically adapts the clock frequency while the master device maintains control, enabling the communication system to adjust to different operating conditions and technological standards.
3Adaptability or versatility
If conventional protocols are used, then interoperability is ensured, but the protocol becomes over-engineered and consumes excessive area
Solution Approach 1:
The patent extracts the clock generation function from the slave device and centralizes it in the master device. This eliminates the need for slave PLL circuitry, reducing the IC area consumed by clock synchronization components while maintaining interoperability through the master-controlled clock distribution architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, saves space, and effectively mitigates EMI by allowing the master clock to change frequency quickly, improving communication efficiency and compliance with FCC emission standards.
Implementation Method 1
a phase-locked loop (PLL) that multiplies a reference clock input to generate a communication link clock signal
Data Source
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AI summary
Systems and methods for chip to chip communication are disclosed. In an exemplary aspect, a chip to chip link comprises a master device having a data transmitter, a clock, a clock transmitter, a phase locked loop (PLL) associated with the clock, and a receiver. The chip to chip link also comprises a slave device that has a data transmitter, a clock receiver, and a data receiver. Noticeably absent from the slave device is a clock or a PLL. By removing the clock from the slave device, the slave device does not have the power consuming element of a slave PLL. Further, because the slave device does not have a clock which would normally have to acquire a new frequency and settle, the master clock may change frequency relatively quickly and vary the frequency across many frequencies, not just one or two predefined frequencies.