Master-Slave Chip Synchronization via Shared Bidirectional Path
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Solution Overview
Problem
Existing communication systems between integrated circuit chips require dedicated unidirectional communication paths, consuming valuable chip real estate and resources, and lack efficient synchronization mechanisms when multiple chips need to coordinate signal events.
Innovation Solution
A master-slave circuit design utilizing a single bidirectional communication path with shared I/O ports, where the first chip to detect a signal event assumes control, allowing both chips to remain synchronized with minimal resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two separate dedicated unidirectional communication paths are used for chip synchronization, then reliable communication between chips is ensured, but chip real estate and operational resources are consumed
Solution Approach 1:
The patent merges two separate unidirectional communication paths into a single bidirectional communication path. The first chip and second chip share the same communication path, with each chip having an I/O pad that can both transmit and receive signals through this shared path, thereby reducing the total number of I/O pads from four to two while maintaining synchronization capability
Solution Approach 2:
The shared communication path serves multiple functions: it enables bidirectional communication for synchronization, allows either chip to initiate communication based on who detects the signal event first, and provides a universal interface that reduces hardware complexity. The I/O pads are configured to be multi-functional, serving both as transmitters and receivers depending on the communication direction
2Reliability
If four I/O ports are used for dedicated communication paths, then clear signal transmission is achieved, but operational resources are consumed
Solution Approach 1:
The patent combines four I/O ports into two shared I/O pads. Each I/O pad can dynamically switch between transmitting and receiving modes based on which chip detected the signal event first, eliminating the need for dedicated transmit and receive ports for each chip while maintaining clear signal transmission through proper timing and control
3Productivity
If a single bidirectional communication path is shared by two chips, then chip resources are conserved, but control conflicts may occur when both chips detect signal events simultaneously
Solution Approach 1:
The patent implements preliminary action by establishing a clear protocol before communication occurs: the chip that detects the signal event first gains control of the shared communication path. This pre-established rule prevents control conflicts by ensuring only one chip transmits at a time, even when both detect events simultaneously. The detecting chip sets the logic state of the I/O pad, and the other chip logically deduces its slave status
Solution Approach 2:
The system uses feedback mechanisms where each chip monitors the logic state of the shared I/O pad to determine communication status. When one chip transmits synchronization information, the other chip receives it and adjusts its operation accordingly. This feedback loop ensures proper coordination and prevents conflicts on the shared path
Data Source
AI summary
A master-slave circuit is disclosed that maintains synchronization between two integrated circuit chips, using minimal chip resources. In one embodiment, a single, bidirectional communication path is shared by the two chips. Meanwhile, only one I/O port on each chip is used to send and receive signals via the bidirectional communication path. The first chip to detect a signal event is designated the master and controls the bidirectional communication path. The master can communicate the status to the other chip by controlling the logic state of the I/O ports. When the second chip detects that the I/O port is controlled by the first chip, the second chip will logically deduce that it is now the slave. If both chips detect the signal event at substantially the same time, one of the two chips is pre-programmed to assume control of the I/O port as the master.