Master-Slave Clock Synchronization for Phase-Controlled Power Dissipation
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Solution Overview
Problem
Current timing systems lack control over time relationships between clock signals generated by integrated electronic devices, limiting the ability to manage overall power dissipation effectively in applications like airbag actuation systems.
Innovation Solution
A timing system with a master and slave configuration, where a microcontroller unit generates synchronization signals to lock the frequencies of local oscillators in both devices, allowing for precise phase shifting and synchronization of clock signals to control power dissipation and electromagnetic emissions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If integrated electronic devices generate clock signals independently using local oscillators, then each device can maintain its timing autonomy, but the time relationships between clock signals from different devices cannot be controlled, limiting overall power dissipation management
Solution Approach 1:
A synchronization device is introduced as an intermediary between multiple integrated electronic devices. This synchronization device generates a reference clock signal that is distributed to all devices, enabling coordinated timing while preserving individual device autonomy. The reference clock acts as a mediator that harmonizes the timing relationships without requiring changes to the individual device architectures.
Solution Approach 2:
The timing control function is segmented into two parts: a central synchronization device that generates the reference clock signal, and individual integrated electronic devices that use this reference signal to generate their own clock signals. This segmentation allows independent timing generation at the device level while maintaining overall synchronization through the shared reference clock.
2Loss of energy
If clock signals are synchronized with controlled phase relationships, then power dissipation can be managed by preventing simultaneous actuation, but the system complexity increases due to synchronization requirements
Solution Approach 1:
The synchronization device receives feedback signals from each integrated electronic device indicating the phase relationship of their clock signals. Based on this feedback, the synchronization device adjusts the reference clock signal to achieve desired phase relationships between devices. This feedback mechanism enables automatic phase control without requiring complex manual synchronization configurations.
Solution Approach 2:
The patent replaces complex mechanical or manual synchronization mechanisms with an electronic feedback-based phase control system. Instead of using physical adjustment mechanisms or manual configuration, the system uses electronic feedback signals and automated phase adjustment to achieve precise timing relationships between devices.
3Productivity
If multiple switching regulators operate simultaneously with independent clock signals, then system functionality is maintained, but power consumption peaks occur due to simultaneous actuation
Solution Approach 1:
The synchronization device implements periodic phase shifting of clock signals distributed to different switching regulators. By introducing controlled phase differences in periodic intervals, the system ensures that regulators do not actuate simultaneously, thereby eliminating power consumption peaks while maintaining continuous operational functionality through the periodic coordination of switching events.
Data Source
AI summary
In an embodiment a timing system includes a master timing device including a master oscillator stage configured to receive a reference signal and to generate a first main clock signal frequency-locked with the reference signal, a master timing stage including a master counter configured to update value with a timing that depends on the first main clock signal, the master timing stage configured to generate a first local clock signal of a pulsed type, a timing of pulses of the first local clock signal being controllable by the master counter and a master synchronization stage configured to generate a synchronization signal synchronous with the first local clock signal, wherein the synchronization signal includes a corresponding pulse for each group of consecutive pulses of the first local clock signal formed by a number (N) of pulses, and a slave timing device including a slave oscillator stage configured to receive the reference signal and to generate a second main clock signal frequency-locked with the reference signal, a slave timing stage and a slave synchronization stage.