Master-Slave Clock Distribution for Radar Phase Coherence
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Solution Overview
Problem
Current cascaded radar systems face challenges in clock distribution and synchronization due to misalignment between clock and frame start timings, particularly under process, voltage, or temperature variations, leading to phase errors that compromise angular resolution and system performance.
Innovation Solution
A master-slave clock distribution method where the frame start signal is embedded within the system clock signal, allowing for quasi-perfect synchronization across devices using a star-routed PCB and low-voltage differential signaling, reducing the need for dedicated pins and relaxing PCB design constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate clock and frame start signals are distributed to multiple devices, then timing control flexibility is improved, but delay mismatch and phase errors increase under PVT variations
Solution Approach 1:
The patent combines the frame start signal and clock signal into a single integrated signal that is distributed to all devices. This merging eliminates the delay mismatch between separate clock and frame start signals that occurs under process, voltage, and temperature variations, while still providing the necessary timing control flexibility through the integrated signal's structure.
2Reliability
If dedicated pins are used for clock and frame start signals, then signal integrity is improved, but device pin count and PCB complexity increase
Solution Approach 1:
The patent makes a single signal pin serve multiple functions by encoding both the frame start indication and clock signal into one distributed signal. This multi-functionality reduces the number of dedicated pins required while maintaining signal integrity through the unified signal path that is less susceptible to PVT variations.
3Manufacturing precision
If strict PCB routing constraints are imposed for clock synchronization, then phase coherence is improved, but PCB design flexibility and ease of manufacture decrease
Solution Approach 1:
By merging the frame start and clock signals into a single distributed signal, the patent reduces the number of critical timing paths that require strict PCB routing control. This approach maintains phase coherence across devices while significantly relaxing the PCB design constraints, allowing for greater manufacturing flexibility and easier implementation.
Data Source
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AI summary
A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784). The at least one master device (710) and at least one slave device (720, 723) each comprise: a demodulator circuit (764, 765) configured to receive the distributed system clock signal (784) and re-create therefrom a synchronized system clock signal (788, 790) used by a respective ADC, (741, 742) of each of the the master device (710) and at least one slave device (720).