Master-Slave Counter Synchronization via Periodic Initialization

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Solution Overview

Problem

Existing data processing systems face challenges in synchronizing distributed counters with a central 'always-on' system counter without causing time inconsistencies or requiring wide, high-speed buses for count value distribution.

Innovation Solution

The implementation of master and slave counter circuitry with fault detection, where the master counter provides initialization and fault detection data via a synchronization connection to ensure that slave counters are accurately synchronized and operate within a threshold count difference, allowing for efficient and consistent timekeeping without continuous distribution of the master count signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If distributed counters are continuously synchronized with the master counter via wide high-speed buses, then synchronization accuracy is improved, but system complexity and power consumption increase

Engineering Contradiction:

Improvesynchronization accuracyVSAvoidsystem complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The slave counter is pre-loaded with the master counter value at initialization and at periodic intervals. This preliminary action ensures that the slave counter starts with an accurate reference value, eliminating the need for continuous high-speed synchronization during normal operation. The pre-loading mechanism maintains synchronization accuracy while reducing system complexity and power consumption.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Instead of continuous synchronization, the system uses periodic updates where the master counter value is transferred to the slave counter at predetermined time intervals. This periodic action maintains adequate synchronization accuracy for time-stamping operations while significantly reducing the bandwidth requirements and complexity of the synchronization mechanism compared to continuous high-speed bus connections.

Inventive Principle:

Principle #19Periodic action

2Measurement precision

If the slave counter is pre-loaded with master counter value, then synchronization accuracy is improved, but the bus width required for continuous distribution is reduced

Engineering Contradiction:

Improvesynchronization accuracyVSAvoidbus width

Core Design Contradiction:

Measurement precisionVSQuantity of substance

Solution Approach 1:

The slave counter is pre-loaded with the master counter value at initialization and periodic intervals. This preliminary action ensures that the slave counter starts with an accurate reference value, eliminating the need for continuous high-speed synchronization during normal operation. The pre-loading mechanism maintains synchronization accuracy while reducing system complexity and power consumption.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Inventive Principle:

Principle #19Periodic action

3Reliability

If fault detection mechanisms are implemented in slave counters, then system reliability is improved, but device complexity increases

Engineering Contradiction:

Improvesystem reliabilityVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The system implements a feedback mechanism where the slave counter monitors its own operation and compares its generated timestamps against expected values based on the master counter. When a discrepancy is detected, the system can identify and correct faults. This feedback-based fault detection improves reliability by enabling error detection and correction while maintaining relatively simple circuitry through intelligent monitoring rather than complex redundant systems.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS10769038B2Counter circuitry and methods including a master counter providing initialization data and fault detection data and wherein a threshold count difference of a fault detection count is dependent upon the fault detection data

Publication Date: 2020.09.08 ARM LTD

AI summary

Apparatus comprises master counter circuitry to generate a master count signal in response to a clock signal; slave counter circuitry responsive to the clock signal to generate a respective slave count signal, the slave counter circuitry having associated fault detection circuitry; and a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry, the master counter circuitry being configured to provide via the synchronisation connection: initialisation data at an initialisation operation; and fault detection data at a fault detection operation; the initialisation data and subsequent fault detection data each representing respective indications of a state of the master count signal; the slave counter circuitry being configured, during an initialisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the initialisation data provided by the master counter circuitry; and the fault detection circuitry associated with the slave counter circuitry being configured, during a fault detection operation for that slave counter circuitry, to detect whether a counting operation of that slave counter circuitry generates a slave count signal which is within a threshold count difference of a fault detection count value dependent upon the fault detection data provided by the master counter circuitry.