Master/Slave Debug Interface for Shared SOC Bus
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Solution Overview
Problem
In System-on-Chip (SOC) designs, the high degree of integration often leads to insufficient Input/Output (IO) signals, making debugging and testing challenging due to pad or IO limitations, especially in environments where space and cost are concerns, and configuring SOCs without debug interfaces becomes problematic.
Innovation Solution
A System-on-Chip (SOC) integrated circuit debugging system where one SOC acts as a master with a bidirectional Master/Slave debug interface, enabling it to send and receive debug data between SOC ICs and an external host system, thereby allowing for shared debug bus usage and eliminating the need for conventional debug tool hardware connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If SOCs are configured without debug interfaces to conserve space and reduce cost, then device complexity and IO usage are reduced, but debugging and testing become problematic or infeasible
Solution Approach 1:
The patent introduces an intermediary debug interface circuit that couples to multiple SOCs through a shared debug bus. This intermediary acts as a mediator between the external debug tool and multiple SOCs, enabling debugging functionality without requiring each SOC to have its own dedicated debug interface, thus conserving IO resources while maintaining debugging capability.
Solution Approach 2:
The shared debug bus and intermediary debug interface are designed to serve multiple SOCs simultaneously. A single debug interface circuit can debug multiple SOCs by multiplexing the debug bus, making the debug infrastructure universal rather than dedicated to each individual SOC, thereby reducing overall system complexity and IO usage.
2Device complexity
If multiple SOCs share one debug bus and connector, then connector pin usage is reduced and synchronous debugging is enabled, but debug interface availability for each SOC is limited
Solution Approach 1:
The debug interface system implements dynamic multiplexing where the shared debug bus can be dynamically allocated to different SOCs as needed. The intermediary debug interface circuit can switch between multiple SOCs, allowing flexible and adaptive access to any SOC on the bus, thus maintaining high interface availability despite the shared configuration.
Solution Approach 2:
The debug interface functionality is segmented into a shared common infrastructure (debug bus) and individual SOC-specific access points through the intermediary circuit. This segmentation allows the system to maintain a simple shared backbone while providing dedicated access pathways to each SOC, balancing simplicity with versatility.
3Adaptability or versatility
If chip size increases to provide more functionality, then system capability is enhanced, but the number of available IO signals becomes insufficient
Solution Approach 1:
The patent merges the debug interface functionality of multiple SOCs into a single shared debug bus infrastructure. By combining individual debug interfaces into a unified shared resource, the system can support enhanced functionality across multiple SOCs without proportionally increasing the total number of IO signals required, as the debug functionality is consolidated rather than replicated.
Data Source
AI summary
A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a master/slave debug interface. The master/slave debug interface on the master SOC IC is a bidirectional debug interface operable to send and receive debug data between the SOC ICs and an external host system.