Parallel Master-Slave Flip-Flop Timing for Reduced Setup Time

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing master-slave flip-flops face challenges in reducing setup time without increasing the area and power consumption or risking read failures, especially when detecting data from memory outputs early.

Innovation Solution

The implementation of a parallel master-slave flip-flop (PMSFF) with a delayed sense enable signal and a NAND gate configuration allows for a shorter setup time, enabling the use of smaller bitcells while maintaining robust differential voltage sensing, thus reducing the risk of read failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If a larger, stronger bitcell is used to increase differential voltage output, then the differential voltage strength is improved, but the area and power consumption increase

Engineering Contradiction:

Improvedifferential voltage strengthVSAvoidbitcell area

Core Design Contradiction:

StrengthVSArea of stationary object

Solution Approach 1:

The patent changes the timing parameter of the sense enable signal by delaying its assertion relative to the bitline assertion. This parameter change allows the bitcell to develop differential voltage over a longer period, enabling smaller bitcells to produce sufficient voltage for reliable detection without increasing area or power consumption.

Inventive Principle:

Principle #35Parameter changes

2Loss of time

If the detection threshold for differential voltage is reduced to enable earlier detection, then the detection speed is improved, but the possibility of read failure increases

Engineering Contradiction:

Improvedetection timeVSAvoidread failure risk

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

The patent performs preliminary action by asserting the sense enable signal after the bitline has already been asserted and has had time to develop differential voltage. This preliminary development of voltage ensures that when detection occurs, the differential voltage is sufficiently robust, maintaining reliability while enabling timely detection.

Inventive Principle:

Principle #10Preliminary action

3Speed

If the sense enable signal is asserted earlier to reduce setup time, then the detection speed is improved, but the differential voltage development time is insufficient

Engineering Contradiction:

Improvedetection speedVSAvoiddifferential voltage development duration

Core Design Contradiction:

SpeedVSDuration of action of moving object

Solution Approach 1:

The patent uses periodic clock signals to control the timing of bitline assertion and sense enable signal assertion. By carefully controlling the phases and durations of these periodic actions, the system ensures that the sense enable signal is asserted at the optimal moment when differential voltage has sufficient time to develop, achieving both speed and reliability.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS8908449B1Master-slave flip-flop with reduced setup time

Publication Date: 2014.12.09 NXP USA INC

AI summary

A master stage (502) of a master-slave flip-flop (500) includes an input terminal (504) for receiving the data-in signal, an output terminal, and terminals for receiving first clock signals, a transmission gate (522) coupled to the input terminal and having an output terminal, a storage element (520) coupled to the output terminal of the transmission gate, and a two-input logic gate (525) having a first input terminal (541) coupled to the storage element, a parallel input terminal (542) coupled to the input terminal of the master stage, and an output terminal (543) that provides an output terminal of the master stage. A slave stage (503) has terminals for receiving second clock signals, wherein first clock signals are delayed relative to second clock signals.