Master-Slave Frequency Locked Loop for Voltage Droop Clocking
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Solution Overview
Problem
Conventional adaptive clocking approaches in integrated circuits fail to effectively compensate for noise-induced voltage variations, leading to timing uncertainties and potential failures due to dependence on average noisy voltages and low frequency noise.
Innovation Solution
A master/slave frequency locked loop configuration decouples PVT tracking from frequency adaptation, using a slave oscillator to respond to high-frequency voltage droops or overshoots while isolating from low-frequency noise, with a master oscillator providing a stable reference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional adaptive clocking approaches use DLL or FLL to lock frequency with system clock, then the clock frequency can be adapted to supply voltage variations, but the system locks to average noisy voltage including low frequency noise, causing timing uncertainty
Solution Approach 1:
The clocking system is segmented into two independent oscillators: a master oscillator that tracks average voltage (including low-frequency noise) for PVT compensation, and a slave oscillator that responds only to high-frequency voltage droops. This segmentation allows each oscillator to serve a specific function, preventing the slave from locking to low-frequency noise while maintaining frequency adaptation capability.
Solution Approach 2:
A frequency control word (FCW) mechanism acts as an intermediary between the master and slave oscillators. The master oscillator generates an FCW based on average voltage conditions, which is then used to control the slave oscillator's frequency. This intermediary allows the slave to adapt to voltage droops through the master's control signal without directly locking to the noisy voltage, thereby reducing timing uncertainty.
2Adaptability or versatility
If the adaptive clock system locks to average noisy voltage, then frequency can be adapted, but dependence on power delivery response causes the system to lock to low frequency noise from temperature or voltage variations
Solution Approach 1:
The system segments the frequency adaptation function from the PVT tracking function. The master oscillator handles PVT tracking by locking to average voltage, while the slave oscillator handles high-frequency droop compensation. This segmentation prevents the slave oscillator from being affected by low-frequency noise, thereby improving frequency stability while maintaining adaptability.
Solution Approach 2:
The slave oscillator is designed with local quality by making its frequency response selective to only high-frequency voltage droops through its specific circuit implementation (e.g., using a frequency-to-voltage converter with high-pass characteristics). This local quality ensures that the slave oscillator responds appropriately to voltage droops without being influenced by low-frequency noise, thus maintaining stable frequency operation.
3Reliability
If clock frequency is lowered in response to voltage droop, then timing margin is increased, but the response depends on power delivery characteristics causing uncertainty
Solution Approach 1:
The frequency control word (FCW) serves as an intermediary that translates master oscillator measurements into slave oscillator control signals. This intermediary mechanism allows the slave oscillator to respond to voltage droops in a standardized way, independent of specific power delivery characteristics, thereby reducing uncertainty while maintaining timing margin.
Solution Approach 2:
The system changes the control parameter from direct voltage-dependent frequency adjustment to FCW-based frequency control. By using the master oscillator's FCW as the control parameter for the slave oscillator, the system achieves a more predictable and standardized response to voltage droops, reducing dependence on variable power delivery characteristics.
Data Source
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AI summary
A master/slave configuration of a frequency locked Loop (FLL) decouples the process, target voltage, temperature (PVT) tracking goals of locking the loop from adapting the clock frequency in response to voltage droops in the supply. A master oscillator circuit receives a regulated supply voltage and supplies a master oscillator signal. A control circuit supplies a master frequency control signal to control a frequency of the master oscillator signal to a target frequency. A slave oscillator circuit is coupled to a regulated supply voltage and a droopy supply voltage and supplies a slave oscillator signal having a frequency responsive to a slave frequency control signal that is based on the master frequency control signal. The frequency of the second oscillator signal is further responsive to a voltage change of the droopy supply voltage.