Master-Slave FLL Clocking for Voltage Droop Response

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional adaptive clocking approaches in integrated circuits, such as those using DLLs or FLLs, lock to average noisy voltages and frequencies, leading to uncertainty due to power delivery and temperature variations, particularly failing to effectively compensate for low-frequency noise and voltage droops.

Innovation Solution

A master/slave configuration of a Frequency Locked Loop (FLL) decouples PVT tracking goals from adapting clock frequency responses to voltage droops or overshoots, using a master oscillator with a regulated supply voltage and a slave oscillator that adjusts frequency based on voltage changes, ensuring stable clock signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a conventional adaptive clocking approach using DLL or FLL is used, then the clock frequency can be adjusted in response to voltage variations, but the system locks to average noisy voltage causing uncertainty and failing to effectively compensate for low-frequency noise and voltage droops

Engineering Contradiction:
Improveadaptive clock frequency adjustmentVSAvoidtiming margin stability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The system segments the adaptive clocking function into two independent oscillators: a master oscillator that locks to the reference clock frequency (providing stable PVT tracking) and a slave oscillator that responds to voltage droops (providing noise compensation). This segmentation allows each oscillator to perform its specialized function without interference, resolving the contradiction between adaptability and reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The master oscillator acts as an intermediary between the reference clock and the slave oscillator. It receives the reference clock signal and generates a master oscillator signal at the target frequency, which then controls the slave oscillator. This intermediary structure filters out low-frequency noise while preserving the ability to respond to voltage droops, simultaneously achieving adaptability and reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If the oscillator locks to average noisy voltage, then frequency control is simplified, but uncertainty increases due to dependence on power delivery response and application characteristics

Engineering Contradiction:
Improvefrequency control simplicityVSAvoidfrequency accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The system applies local quality by giving each oscillator a different supply voltage characteristic: the master oscillator receives a clean regulated voltage for accurate frequency control, while the slave oscillator receives the noisy droopy voltage to detect voltage droops. This localized differentiation allows simple frequency control through the master while achieving high frequency accuracy through the slave's response to actual voltage conditions.

Inventive Principle:
Principle #3Local quality

3Reliability

If the clock frequency is lowered in response to voltage droop, then timing margins are improved, but the system becomes dependent on average voltage locking which reduces effectiveness for low-frequency noise

Engineering Contradiction:
Improvetiming marginVSAvoidresponse to voltage variations
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The system implements dynamics by making the slave oscillator's frequency dynamically responsive to instantaneous voltage droops while the master oscillator maintains a stable locked frequency. The slave oscillator can quickly adjust its frequency in response to voltage variations without being constrained by the averaging effect of conventional single-oscillator systems, achieving both reliability and adaptability simultaneously.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10425089B2Master/slave frequency locked loop
Publication Date: 2019.09.24 ADVANCED MICRO DEVICES INC
  • US10425089B2 patent drawing
  • US10425089B2 patent drawing
  • US10425089B2 patent drawing

AI summary

A master/slave configuration of a frequency locked Loop (FLL) decouples the process, target voltage, temperature (PVT) tracking goals of locking the loop from adapting the clock frequency in response to voltage droops in the supply. A master oscillator circuit receives a regulated supply voltage and supplies a master oscillator signal. A control circuit supplies a master frequency control signal to control a frequency of the master oscillator signal to a target frequency. A slave oscillator circuit is coupled to a regulated supply voltage and a droopy supply voltage and supplies a slave oscillator signal having a frequency responsive to a slave frequency control signal that is based on the master frequency control signal. The frequency of the second oscillator signal is further responsive to a voltage change of the droopy supply voltage.