Master-Slave Level Shifter Array for Known Power-Up States

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Solution Overview

Problem

Conventional level shifters face challenges in ensuring a known start-up state and high-speed operation while maintaining density, as they often require asymmetrical designs that increase silicon wafer area and production costs.

Innovation Solution

A master level shifter with an asymmetrical design generates an enable signal to control symmetrical slave level shifters, ensuring a known power state during power transitions and reducing wafer area size by using a one-sided NMOS latch and unbalanced drivers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If asymmetrical level shifter designs are used to ensure a known start-up state, then reliability is improved, but device area increases

Engineering Contradiction:

Improveknown start-up stateVSAvoidsilicon wafer area

Core Design Contradiction:

ReliabilityVSArea of moving object

Solution Approach 1:

The level shifter is divided into two functional segments: a master level shifter that ensures a known start-up state through asymmetrical design, and multiple slave level shifters that can be symmetrical and minimal in size. The master generates control signals that drive the slaves, allowing the system to achieve reliability without requiring all units to be large and asymmetrical.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Instead of making all level shifters asymmetrical to ensure known start-up states, the invention inverts the approach by using a single asymmetrical master to control multiple symmetrical slaves. The master's asymmetrical design ensures the known state, while the slaves follow the master's control signals, reversing the conventional wisdom that each unit must be independently asymmetrical.

Inventive Principle:

Principle #13The other way round (Inversion)

2Speed

If pull-down transistors are made relatively large to flip latch state quickly, then operation speed is improved, but device area increases

Engineering Contradiction:

Improvelatch state transition speedVSAvoidtransistor area

Core Design Contradiction:

SpeedVSArea of moving object

Solution Approach 1:

The functionality of large pull-down transistors is segmented between the master and slave level shifters. The master contains the asymmetrical design with appropriately sized transistors to ensure quick state transitions and generate control signals. The slaves use minimal-sized transistors since they are driven by the master's control signals, achieving fast operation without requiring large transistor areas in each unit.

Inventive Principle:

Principle #1Segmentation

3Area of moving object

If symmetrical slave level shifters are used to reduce area, then device density is improved, but control of known power state becomes difficult

Engineering Contradiction:

Improvewafer area per slave shifterVSAvoidpower state control

Core Design Contradiction:

Area of moving objectVSReliability

Solution Approach 1:

The master level shifter acts as an intermediary that provides control signals to the symmetrical slave level shifters. The master ensures the known power state through its asymmetrical design and uses these control signals to drive the slaves, allowing the symmetrical slaves to maintain their minimal area while still achieving reliable power state control through the master's mediation.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10256796B2Master-slave level shifter array architecture with pre-defined power-up states

Publication Date: 2019.04.09 QUALCOMM INC

AI summary

A master-slave level shifter array includes an asymmetric master level shifter having a predefined output state that produces an enable signal to drive an array of symmetric slave level shifters during a power collapse. As a result, the slave level shifter array has a reliable output state during a power collapse, while also providing wafer area savings due to their small symmetric characteristics.