Master-Slave Level Shifter Latch for Memory Word Line Decoder
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Solution Overview
Problem
Conventional word line decoder and driver path architectures in computing systems experience significant propagation delays, hindering the speed of memory devices and necessitating an improvement to enhance memory access times.
Innovation Solution
The implementation of a master-slave level shifter latch and driver configuration, which receives decoded address signals on a clock signal's first state, latches them on the second state, and outputs word line signals with a greater potential difference, along with a transmission gate structure that isolates and couples latches to achieve level shifting and drive word lines efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional word line decoder and driver path architecture is used, then the circuit can be implemented with standard components, but the propagation delay is significant and memory speed is limited
Solution Approach 1:
The patent combines the level shifting function and the latch function into a single integrated master-slave latch circuit. The master latch receives decoded address signals and performs level shifting from low voltage to high voltage potential, while the slave latch captures and holds these signals. This merging eliminates the need for separate level shifters and reduces the number of discrete components in the critical signal path, thereby reducing propagation delay and improving memory access speed
Solution Approach 2:
The master latch performs level shifting of the decoded address signals before they are latched by the slave latch. By preparing the signals at the appropriate voltage level in advance (during the first clock phase), the subsequent latching operation can proceed more quickly without waiting for voltage level conversion. This preliminary action optimizes the timing and reduces overall propagation delay
2Ease of operation
If clocked flip flops are used for latching, then the circuit can maintain synchronous operation, but the device complexity and area increase
Solution Approach 1:
Instead of using conventional clocked flip-flops that require complex clocking logic and multiple gates, the patent employs a master-slave latch structure controlled by complementary clock phases. The master latch is enabled during the first clock phase and the slave latch during the second phase, eliminating the need for edge-triggered flip-flop logic. This inversion of the conventional approach maintains synchronous operation while significantly reducing circuit complexity and device area
Solution Approach 2:
The latching function is segmented into two distinct stages: the master latch and the slave latch. Each latch is simpler in structure than a full flip-flop, and they operate in sequence during different clock phases. This segmentation allows the circuit to achieve synchronous operation with simpler, more area-efficient latch elements rather than complex flip-flops
Data Source
AI summary
A clocked driver circuit can include a master-slave level shifter latch and a driver. The master-slave level shifter latch can be configured to receive an input signal upon a first state of a clock signal, latch the input signal upon a second state of the clock signal and generate a level shifted output signal corresponding to the latched input signal. The driver can be configured to receive the level shifted output signal from the master-slave level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.