Master-Slave Memory Architecture for Circuit Size Reduction
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Solution Overview
Problem
Conventional data transfer systems with multiple devices or circuit blocks sharing a memory require memory control circuits and access control circuits, leading to increased circuit complexity and size, as each device or block needs to manage memory access independently.
Innovation Solution
Reversing the roles of devices/circuit blocks and memory, where the memory acts as a master outputting addresses and data in synchronization with a clock, and each device/circuit block serves as a slave with decoders and registers to receive data, eliminating the need for memory control and access control circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If each device or circuit block has a memory control circuit for reading data, then data can be read from memory, but circuit size increases
Solution Approach 1:
The patent extracts the memory control functionality from individual devices/circuit blocks and consolidates it into a single memory control circuit on the memory side. This eliminates the need for each device to have its own control circuit, thereby reducing overall circuit size while maintaining data reading capability.
Solution Approach 2:
The memory control circuit on the memory side serves all devices and circuit blocks simultaneously, providing universal control functionality. This single circuit replaces multiple individual control circuits, reducing total circuit area while enabling all devices to read data from memory.
2Reliability
If an access control circuit is mounted on the memory side to handle simultaneous accesses, then access collision is avoided, but circuit size increases
Solution Approach 1:
The patent combines the access control functionality with the memory control circuit on the memory side, merging multiple control functions into a single integrated circuit. This eliminates the need for separate access control circuits while maintaining collision avoidance capability, thereby reducing overall circuit size.
Solution Approach 2:
The memory control circuit on the memory side performs multiple functions including both data reading control and access collision avoidance. This multi-functional approach eliminates the need for separate dedicated access control circuits, reducing total circuit area while maintaining reliability.
3Ease of operation
If memory control and access control circuits are mounted, then memory access is controlled, but device complexity increases
Solution Approach 1:
The patent extracts control functionality from individual devices and centralizes it on the memory side. This reduces the complexity of each device by removing control circuits from them, while the centralized memory control circuit handles all control operations.
Solution Approach 2:
Instead of having devices control memory access, the patent inverts the control relationship by having the memory control devices. This role reversal simplifies device complexity while maintaining effective memory access control through the centralized memory control circuit.
Data Source
AI summary
The invention is directed to decreasing a circuit size of a system in which a plurality of devices or circuit blocks share and use one memory. A system is configured so that a memory block serves as a master and each of circuit blocks serves as a slave, and thus the slave side (the circuit blocks) receives necessary data from the memory block by only having decoders corresponding to addresses assigned thereto in advance and registers. In this case, since the registers have been also needed in a conventional system in order to hold data read out from a memory, the circuit size decreases in the whole system. Since this effect is enhanced in proportion to the number of the circuit blocks sharing the memory block, the effect is enhanced as the system size increases.