Wafer-Level Memory Testing with Master-Slave Power Sharing
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Solution Overview
Problem
The testing of nonvolatile memory chips without a power circuit is complex and costly due to the need for external power and voltage sources, leading to increased manufacturing expenses and the risk of failed memory systems from undetected 'bad' chips during final packaging.
Innovation Solution
A semiconductor wafer layout where master chips with power supply or control circuits are arranged in rows, and slave chips with memory cell arrays are arranged in columns, allowing for wafer-level testing with shared power and control signals, reducing the need for external testing equipment and enabling early identification of defective chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If nonvolatile memory chips are configured without a power circuit to reduce area and power consumption, then area and power consumption are reduced, but testing complexity and cost increase due to the need for external power and control circuits
Solution Approach 1:
The patent merges multiple master chips (providing power and control signals) and slave chips (memory chips without power circuits) onto a single wafer, creating an integrated testing structure. This allows the memory chips to be tested using the shared power and control circuits of the master chips, reducing individual chip area while maintaining testing capability through the combined wafer-level structure.
Solution Approach 2:
The master chips serve multiple functions: they provide power supply circuits, generate control signals, and enable testing of multiple slave chips simultaneously. This multi-functional design allows a single master chip to support multiple memory chips during testing, reducing the need for separate external testing equipment for each chip.
2Reliability
If external testers are used to provide power and control signals for testing memory chips without power circuits, then testing can be performed, but manufacturing cost increases due to expensive testing apparatuses
Solution Approach 1:
The patent combines multiple chips on a single wafer with shared power and control circuits, enabling batch testing of multiple memory chips using a single testing setup. This wafer-level integration reduces the need for multiple expensive external testers, thereby lowering manufacturing costs while maintaining comprehensive testing capability.
Solution Approach 2:
The master chips on the wafer provide self-service by generating their own control signals and power supply voltages, eliminating the need for complex external testing equipment. The integrated circuits on the wafer serve themselves by providing the necessary power and control functions that would otherwise require separate external devices.
3Ease of manufacture
If testing is performed only after packaging, then packaging process is simplified, but manufacturing yield decreases due to undetected defective chips causing system failure
Solution Approach 1:
The patent performs testing at the wafer level before the packaging process, allowing defective chips to be identified and removed early in manufacturing. This preliminary testing action enables sorting of good and bad chips before packaging, ensuring that only functional chips are packaged and assembled into final memory systems, thereby improving manufacturing yield.
Solution Approach 2:
The wafer is divided into multiple independently testable chip regions, each with its own memory cells that can be individually evaluated. This segmentation allows for precise identification of defective chips without affecting the testing or packaging of adjacent good chips, enabling selective removal of only the defective units.
Data Source
AI summary
A plurality of master chips are arranged in a row on the wafer, each master chip including a power supply circuit providing a power supply voltage, and a plurality of slave chips are arranged in a column to at least one side of a corresponding master chip among the plurality of master chips, each slave chip including a memory cell array functionally operative in response to the power supply voltage provided by the corresponding master chip during wafer level testing.