Master-Slave Flip-Flop Partial Pass Gate for Low-Voltage Hold
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Solution Overview
Problem
Existing master-slave flip-flop memory circuits face challenges in maintaining low voltage nominal hold and variability characteristics, leading to erratic transistor behavior and increased power consumption, which can result in thermal failures and spurious signals.
Innovation Solution
A re-architectured transistor layout is introduced, reducing the number of transistors in the nominal hold critical path by coupling the input of the master latch to a low output of the test switch around a partial pass gate, and using clock and reset enabled inverters to improve stability without increasing circuit area or dynamic power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the source voltage is decreased to prevent thermal failure, then power consumption is reduced, but transistor behavior becomes more erratic as threshold voltage approaches source voltage
Solution Approach 1:
The patent modifies the transistor layout and circuit architecture to optimize voltage distribution and signal paths, enabling stable operation at lower source voltages without causing erratic transistor behavior. This involves changing the configuration of transistors in the critical path to maintain proper voltage margins.
Solution Approach 2:
The patent introduces intermediate signaling paths and buffer stages that mediate between the low voltage source and the transistor gates, ensuring that threshold voltage effects do not cause instability. The master-slave latch architecture with controlled signal propagation acts as an intermediary to maintain reliability.
2Productivity
If switching speed is increased to improve circuit performance, then productivity is improved, but power consumption increases leading to thermal failure risk
Solution Approach 1:
The patent employs periodic clocked operation with master and slave latches that switch in alternating phases. This periodic action allows the circuit to achieve high effective switching speed while distributing power consumption over time, preventing thermal buildup during any single switching event.
Solution Approach 2:
The circuit uses dynamic voltage switching and clocked control to enable fast switching when needed while allowing power management during stable states. The dynamic operation of the master-slave latch configuration optimizes the balance between switching speed and power consumption.
3Reliability
If the number of transistors in the critical path is reduced to improve low voltage hold characteristics, then reliability is improved, but circuit area may be affected
Solution Approach 1:
The patent merges certain transistor functions and shares circuit elements between different signal paths. By combining functions and eliminating redundant transistors in the critical hold path, the circuit achieves improved low voltage characteristics while maintaining compact area through efficient resource sharing.
Solution Approach 2:
The patent designs transistors and circuit elements to serve multiple functions simultaneously. The same transistor structure is used for both signal transmission and hold function, and the master-slave latch configuration reuses circuit elements across different operational phases, reducing the total transistor count without sacrificing area efficiency.
Data Source
AI summary
The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.