Master-Slave Interleaved BCM PFC Controller Phase Shift
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Solution Overview
Problem
Current power factor correction (PFC) controllers face challenges in maintaining the boundary conduction mode (BCM) state, especially when affected by interference factors, leading to unstable operation and potential harm to the power grid due to incorrect phase shifts in master-slave interleaved PFC circuits.
Innovation Solution
A master-slave interleaved BCM PFC controller is implemented, using phase shifters to generate delayed opening and shutdown signals for the slave channel, ensuring it is activated only when the inductor current reaches zero, and deactivated accordingly, thereby maintaining the BCM state and recovering stability quickly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PFC controllers are used in master-slave interleaved PFC circuits, then the circuit can operate, but the BCM state cannot be maintained stably under interference factors
Solution Approach 1:
The patent employs feedback mechanisms by detecting the inductor current zero-crossing signal and using it to trigger the slave channel controller. The controller continuously monitors the current state and adjusts the control signals accordingly, ensuring the BCM state is maintained even when interference factors are present. This closed-loop control allows the system to recover stability quickly after disturbances.
Solution Approach 2:
The patent applies preliminary action by using phase shifters to generate delayed opening and shutdown signals in advance. The slave channel is pre-configured to activate only when specific conditions are met (inductor current reaches zero and delayed opening signal is active), ensuring proper timing and preventing instability before it occurs.
2Ease of operation
If phase shift control is applied in master-slave interleaved PFC circuits, then channel coordination is achieved, but incorrect phase shifts cause unstable operation
Solution Approach 1:
The patent replaces traditional mechanical or fixed phase shift control with an electronic control mechanism based on signal processing. Phase shifters are used to electronically adjust the timing of control signals, and the slave channel controller uses logical conditions (AND gate operation between delayed opening signal and zero-crossing signal) to determine channel activation, ensuring precise and reliable phase coordination.
Solution Approach 2:
The patent dynamically adjusts the phase shift parameters through electronic control. The phase shifters modify the timing characteristics of control signals based on real-time circuit conditions, allowing the system to maintain optimal phase relationships between master and slave channels while adapting to changing operating conditions and interference factors.
3Productivity
If the slave channel is activated without precise timing control, then the PFC circuit can operate, but harmonics increase and power factor correction efficiency decreases
Solution Approach 1:
The patent implements periodic action through interleaved operation of master and slave channels. The slave channel is activated periodically when its control conditions are met (delayed opening signal active and inductor current zero-crossing signal active), creating a complementary switching pattern that reduces harmonics and improves power factor correction efficiency while maintaining continuous power processing.
Data Source
AI summary
The present invention relates to a master-slave interleaved BCM PFC controller for controlling a PFC circuit with master and slave channels. In one embodiment, the PFC controller can include: a master channel controller that generates a master channel control signal and an inverted master channel control signal; a first phase shifter that provides a first phase shift for the master channel control signal, and generates a delayed opening signal therefrom; a second phase shifter that provides a second phase shift for the inverted master channel control signal, and generates a delayed shutdown signal therefrom; a slave channel controller that receives the delayed opening signal, the delayed shutdown signal, and a slave channel inductor current zero-crossing signal, and generates a slave channel control signal therefrom.