Master-Slave PLL Synchronization for Multi-Chip Clock Alignment

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Solution Overview

Problem

Existing multi-channel PLL systems face challenges in achieving accurate synchronization and efficient resource utilization due to complex designs, high silicon and board area requirements, and impractical timing closure in multi-chip or multi-die environments, leading to cost disadvantages and technical difficulties in proper synchronization and output clock alignment.

Innovation Solution

A master-slave concept with a novel synchronization method that separates digital phase locked loop (DPLL) functions from frequency synthesis functions, using a master device to control multiple slave devices with a serial interface for frequency and phase control, eliminating the need for external feedback and minimizing interconnection lines, while ensuring precise phase and frequency alignment among output clocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a high integration multi-channel PLL device is used to cover all required channels, then the number of channels is sufficient, but the silicon and board area becomes excessively large

Engineering Contradiction:

Improvenumber of channelsVSAvoidsilicon and board area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The system is divided into a master PLL device that contains control logic and one or more slave PLL devices that contain frequency synthesis engines. The master device manages channel configuration and synchronization, while slave devices perform frequency synthesis locally. This segmentation allows the system to support multiple channels without requiring all channels to be present in a single large device, thereby reducing silicon and board area while maintaining adaptability.

Inventive Principle:

Principle #1Segmentation

2Area of stationary object

If devices with a small number of PLL channels are used, then the silicon area is reduced, but technical difficulties arise in synchronization and output clock alignment

Engineering Contradiction:

Improvesilicon areaVSAvoidsynchronization and output clock alignment

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The master PLL device receives feedback from slave devices through feedback clocks that carry phase and frequency information. The master device uses this feedback to adjust and synchronize the output clocks of slave devices, ensuring accurate alignment. This feedback mechanism enables reliable synchronization across multiple small-channel devices without requiring complex manual calibration.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The master PLL device acts as an intermediary between the reference clock source and the slave frequency synthesis engines. It receives the reference clock, performs initial phase-locked loop operations, and then distributes synchronized clock signals to multiple slave devices. This intermediary role simplifies the synchronization complexity that would otherwise exist between multiple independent small-channel devices.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Measurement precision

If an external feedback concept similar to NCO is used for master-slave synchronization, then frequency and phase errors can be corrected, but the design becomes too complex and uses too many pins and resources

Engineering Contradiction:

Improvefrequency and phase error correctionVSAvoiddesign complexity and resource usage

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The complex feedback control logic and NCO (Numerically Controlled Oscillator) functionality are extracted from the slave devices and consolidated into the master PLL device. Slave devices only need to provide simple feedback clocks, while the master device handles all the complex frequency and phase error correction calculations. This extraction significantly reduces the pin count and resource requirements of slave devices while maintaining precise frequency and phase control.

Inventive Principle:

Principle #2Taking out (Extraction)

4Manufacturing precision

If direct control of slaves by master is implemented, then timing control is improved, but strict timing closure requirements become impractical in multi-chip or multi-die environments

Engineering Contradiction:

Improvetiming controlVSAvoidtiming closure in multi-chip or multi-die environment

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The master PLL device performs preliminary timing synchronization by establishing phase-locked relationships with slave devices before actual operation begins. Synchronization parameters and timing relationships are pre-configured and loaded into slave devices during initialization. This preliminary action allows the system to operate with relaxed timing requirements during normal operation, making multi-chip and multi-die implementations practical.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10007639B2PLL system with master and slave devices

Publication Date: 2018.06.26 MICROSEMI SEMICON

AI summary

A master phase locked loop device is operable in association with one or more slave devices including slave digitally controlled oscillators (sDCOs), one or more digital PLL (DPLL) channels include a master digitally controlled oscillator (mDCO). A master synchronization timer generating master timing pulses to read phase and frequency information from the mDCO(s). A peripheral interface sends the read frequency and phase information to the one or more slave devices. A synchronization interface sends the master timing pulses to synchronize a replica synchronization timer in the sDCO(s) that generates slave timing pulses for use in updating the phase and frequency information received at the slave device(s).