Master-Slave Ring Buffer for Multi-Chip Data Synchronization
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Solution Overview
Problem
In color digital complex machines, the synchronization of image data from multiple color channels is challenging due to variations in internal operation clocks, leading to desynchronization issues and increased memory costs when using multiple image processing ASICs with PLL oscillators.
Innovation Solution
Implementing a master-slave relationship between data processing units with a ring buffer, where one ASIC acts as a master and others as slaves, using a synchronizing signal to synchronize output data and reduce memory costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple image processing ASICs with PLL oscillators are used to process different color channels, then processing speed is improved, but synchronization between color channels deteriorates due to variations in internal operation clocks
Solution Approach 1:
A ring buffer is introduced as an intermediary component between multiple image processing ASICs to buffer and synchronize output data from different color channels. The ring buffer absorbs timing variations caused by PLL oscillator differences, ensuring that data from Y, M, C, and K channels are properly synchronized before being read out by the data output synchronizing circuit.
2Reliability
If memory is added to synchronize output data from multiple color channels, then synchronization is improved, but cost increases
Solution Approach 1:
The ring buffer serves multiple functions: it acts as a data buffer for asynchronous data from different color channels, provides timing alignment, and enables synchronized readout. This multi-functional approach achieves synchronization without requiring separate memory components for each color channel, thereby controlling costs.
3Reliability
If a data output synchronizing circuit is added to synchronize data from multiple ASICs, then synchronization is improved, but device complexity increases
Solution Approach 1:
The data output synchronizing circuit combines multiple asynchronous data streams from different color channels into a single synchronized output. By merging the synchronization function into a dedicated circuit that works in conjunction with the ring buffer, the system achieves coordination without requiring complex control logic in each individual ASIC.
Data Source
AI summary
A ring buffer is provided in the data holding section A3 of a data processing section 100A. A master-slave relationship between a plurality of data processing sections 100A, 100B is set. A data output synchronizing signal of the data processing section 100A acting as a master is supplied to the data processing section 100B acting as a slave. This makes it possible to synchronize the output data of the individual data processing sections, while suppressing the memory cost. Input connection terminals (A1) take in object data, an object data enable signal (INHDEN) from the outside, and an object read clock (IMCLK) from the outside. A data holding section (A3) stores object data on the basis of an internal clock. A synchronizing circuit (A4) reads the stored object data on the basis of INHDEN and IMCLK. An output connection terminal (A2) outputs output object data, INHDEN, and an internal clock equivalent to IMCLK to the outside.