Master-Slave Server Architecture for BMC Error Recording
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Solution Overview
Problem
Existing server architectures with BIOS and BMC face challenges in recording error information when errors occur in both the system and BMC, and they incur high hardware costs due to the need for a single BMC across multiple servers.
Innovation Solution
A server with a master-slave architecture that uses memories to record triggering event and system error information, eliminating the need for a BMC at each node by employing a master-node and multiple slave-nodes connected through a multi-path selector, where the master-node and slave-nodes have their own BIOS and memory systems, and the baseboard management controller can access both master-node and slave-node memories via a system management bus interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single BMC is used across multiple servers in a rack, then hardware costs are reduced, but the ability to record error information is compromised when BMC errors occur
Solution Approach 1:
The patent divides the error recording function into two independent parts: BIOS-level recording (using CMOS memory) and BMC-level recording (using SPI flash). This segmentation allows error information to be captured at the BIOS level even when the BMC fails, ensuring reliable error recording while maintaining cost-effective single-BMC architecture.
Solution Approach 2:
The patent implements preliminary error recording by the BIOS into CMOS memory before the system hands over control to the OS or before BMC errors occur. This preliminary action ensures that error information is captured and preserved independently of BMC status, maintaining reliability while using only one BMC per server.
2Productivity
If BIOS passes control to OS after boot completion, then system operation is enabled, but error recording capability is lost when system enters SMM mode
Solution Approach 1:
The BIOS performs preliminary error detection and records error information into CMOS memory before passing control to the OS or entering SMM mode. This ensures error information is preserved in a persistent storage medium that remains accessible even after BIOS control is relinquished, maintaining both system productivity and error information integrity.
Solution Approach 2:
The patent introduces CMOS memory as an intermediary storage medium between the BIOS error detection mechanism and the BMC/IPMI error recording system. This intermediary ensures error information is captured and preserved independently of the OS or SMM state, allowing continuous system operation while maintaining error recording capability.
3Reliability
If multiple BMCs are deployed in each server node, then error recording reliability is improved, but hardware costs increase significantly
Solution Approach 1:
The patent segments the error recording function across two levels: BIOS-level recording using CMOS memory and BMC-level recording using SPI flash. This segmentation eliminates the need for multiple BMCs while maintaining reliable error recording, as the BIOS-level CMOS storage provides a fallback when BMC errors occur.
Solution Approach 2:
The patent creates a copy of error information in CMOS memory by the BIOS, independent of the BMC's SPI flash storage. This copying mechanism ensures error information is preserved in at least one location even if the BMC fails, achieving high reliability without requiring multiple BMC hardware components.
Data Source
AI summary
A server with a master-slave architecture and a method of reading and writing information thereof provided by the present disclosure include a master node, a multi-path selector and at least two slave nodes. Each slave node is connected to the master node through the multi-selector. The slave node includes a slave-node BIOS and a slave-node memory. The slave-node BIOS is configured to record slave-node information in the slave-node memory. The master node includes a master-node BIOS, a master-node memory and a baseboard management controller. The master-node BIOS is configured to record master-node information in the master-node memory. The baseboard management controller is configured to access the master-node memory and decide to access the slave-node memory of one of the slave nodes through the multi-path selector.