Master-Slave TMIC Synchronization for Display Data Output
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Solution Overview
Problem
Display devices with multiple Timing Controller Integrated Circuits (TMICs) face synchronization issues due to frequency deviations in clock signals, leading to unsynchronized data output and difficulties in displaying a natural black screen when abnormal display signals are inputted.
Innovation Solution
A driving control circuit is implemented, featuring an oscillator for generating clock signals, a source driver IC for recovering data and enabling signals, and a timing controller that adjusts the gate output enable signal to synchronize data output across TMICs, ensuring proper data synchronization and display.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple TMICs are used to drive the display panel, then the display device can achieve larger and thinner design, but frequency deviation between oscillators causes data synchronization issues
Solution Approach 1:
The system divides the timing control function across multiple independent TMIC modules, each with its own oscillator. The master TMIC generates reference timing signals that are distributed to slave TMICs, allowing each module to operate semi-independently while maintaining overall synchronization through the master-slave architecture.
Solution Approach 2:
The system implements a feedback mechanism where the master TMIC's timing signals serve as reference for slave TMICs. The slave TMICs receive and synchronize to these reference signals, creating a feedback loop that maintains frequency alignment across all modules despite individual oscillator variations.
2Device complexity
If timing controller is merged with source driver, then device complexity is reduced, but frequency deviation prevents proper black screen display during abnormal signals
Solution Approach 1:
The TMIC module is designed to perform multiple functions: normal display operation, abnormal signal detection, and black screen generation. The same hardware circuitry that drives normal display also handles abnormal signal conditions, eliminating the need for separate control paths while maintaining reliability through unified timing control from the master TMIC.
Solution Approach 2:
The system proactively handles abnormal signals by detecting them and immediately switching to black screen generation mode. The master TMIC continuously monitors signal validity and prepares black screen data in advance, ensuring seamless transition without display artifacts when abnormal conditions are detected.
3Adaptability or versatility
If each TMIC uses its own oscillator, then design flexibility is improved, but clock signal frequency deviation causes unsynchronized data output
Solution Approach 1:
The master TMIC acts as an intermediary that translates and distributes timing signals to all slave TMICs. This intermediary role ensures that despite each slave having its own oscillator, they all synchronize to the master's timing, maintaining data output synchronization while preserving design flexibility.
Solution Approach 2:
The system creates an equipotential timing environment where all slave TMICs operate at the same effective frequency by locking to the master's clock signals. This equalizes the timing potential across all modules, ensuring synchronized data output despite individual oscillator frequency variations.
Data Source
AI summary
The present invention aims to provide a driving control circuit of a display device, which includes a plurality of data driving circuits each having a timing controller merged with a source driver. The data driving circuits are configured to synchronize data of the respective data driving circuits and compensate for a difference between a data enable signal and a gate output enable signal, when an abnormal display signal is received.