Master Time of Day Processor Selection for Redundant Topologies

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Solution Overview

Problem

In symmetric multiprocessor systems, maintaining uniform time across all processors is challenging due to the risk of TOD failures, which can disrupt timing synchronization and workload management.

Innovation Solution

A system dynamically selects a master Time of Day (TOD) processor and assigns an alternate master TOD processor based on specific criteria, such as node location and oscillator connection, to ensure resilience against TOD failures and facilitate seamless failover to a backup topology.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single master TOD processor is designated in a TOD topology, then the system can maintain uniform time across processors, but the system becomes vulnerable to TOD failures and lacks redundancy

Engineering Contradiction:
ImproveTOD failure resilienceVSAvoidTOD topology complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system pre-configures multiple TOD topologies with designated master and alternate master processors before failures occur. When a failure is detected, the system can immediately switch to a pre-prepared alternate topology, eliminating the need for complex runtime selection logic and reducing failover time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically changes the active TOD topology configuration based on failure detection. By switching between different topology configurations (primary vs. alternate), the system adapts to failure conditions while maintaining uniform time across processors, resolving the contradiction between reliability and complexity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the system implements backup TOD topologies for redundancy, then the probability of successful failover increases, but the system complexity and configuration overhead increase

Engineering Contradiction:
ImproveTOD failover success probabilityVSAvoidTOD topology configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system divides the TOD infrastructure into separate, independent topologies (primary and alternate), each with its own master processor and processor set. This segmentation allows failures in one topology to be isolated and does not affect the other, providing redundancy without requiring complex inter-dependent configurations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system creates an alternate TOD topology that mirrors the structure and functionality of the primary topology. This copy provides a ready-to-use backup configuration that can be activated immediately upon failure detection, avoiding the need for complex runtime configuration generation while ensuring redundancy.

Inventive Principle:
Principle #26Copying

3Reliability

If the system dynamically reconfigures TOD topology upon failure detection, then system resilience against errors increases, but the time to restore timing synchronization may increase

Engineering Contradiction:
ImproveSystem error resilienceVSAvoidTOD synchronization restoration time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

By pre-configuring alternate TOD topologies with designated master processors before failures occur, the system eliminates runtime configuration delays. When a failure is detected, the switch to the alternate topology is immediate, minimizing the time loss for restoring timing synchronization while maintaining high reliability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10540244B2Selecting master time of day for maximum redundancy
Publication Date: 2020.01.21 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10540244B2 patent drawing
  • US10540244B2 patent drawing
  • US10540244B2 patent drawing

AI summary

An approach is provided in which a system selects a first processor as a master Time of Day (TOD) processor in a first TOD topology in response to determining that the first processor is directed connected to an oscillator. The system then assigns a second processor as an alternate master TOD processor to a second TOD topology based upon determining that the second processor is on a different node than the first processor. The system configures to the first TOD topology and, when the system detects a TOD failure, the system re-configures to the second TOD topology.