Master Word Line Driver Sharing for Memory Bank Area Reduction
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Solution Overview
Problem
Existing memory device architectures are inefficient due to the substantial size of word line drivers required for accessing multiple banks or portions of memory cells, which increases the overall size of the memory device.
Innovation Solution
The proposed solution involves sharing components of the master word line driver between different portions or banks of memory devices, utilizing a single pre-stage driver for multiple banks and final stage drivers for each bank or portion, to reduce the size and complexity of the word line driver circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate master word line drivers are provided for each bank of memory devices, then each bank can be accessed independently and reliably, but the overall size of the word line driver circuitry increases substantially
Solution Approach 1:
The patent combines multiple master word line drivers into a single shared driver that can be selectively coupled to different banks through switching circuitry. This merging approach reduces the total number of master drivers from multiple separate units to one unified unit, thereby reducing the word line driver area while maintaining the ability to independently access each bank through the switching mechanism.
Solution Approach 2:
The shared master word line driver is designed to perform multiple functions by being selectively coupled to different banks of memory devices. This single driver can serve multiple banks sequentially or in parallel through the switching circuitry, making it a universal component that replaces multiple bank-specific drivers, thus reducing overall circuitry area while maintaining reliable access to all banks.
2Productivity
If multiple master word line drivers are used to access multiple banks simultaneously, then access operations can be performed in parallel across banks, but the device complexity and overall size increase
Solution Approach 1:
By merging multiple master word line drivers into a single shared driver with switching capability, the patent reduces device complexity while maintaining parallel access productivity. The switching circuitry enables the single driver to be dynamically allocated to different banks, allowing parallel operations without requiring multiple permanent driver units, thus simplifying the overall device architecture.
Solution Approach 2:
The patent introduces dynamic switching capability that allows the master word line driver to be flexibly allocated to different banks based on access requirements. This dynamic allocation mechanism enables parallel access operations while keeping the driver circuitry complexity manageable, as the switching logic is simpler than having multiple independent master drivers with all their associated control circuitry.
Data Source
AI summary
Methods, systems, and devices for driver sharing between banks or portions of banks of memory devices are described. An apparatus may include a first bank and a second bank of memory cells and a word line driver configured to activate word lines. The word line driver may include a master word line driver and an address driver. In some examples, the master word line driver may be configured to generate a first signal to a first portion of the first bank or a second portion of the first bank as part of performing an access operation. In some examples, the master word line driver may be configured to generate a first signal for the first bank or the second bank as part of performing an access operation. The address driver configured to generate a second signal to a portion of the first bank or the second bank.