Match Processing Unit Pipeline for Stall-Free Packet Actions
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Solution Overview
Problem
Network switches face challenges in performing packet processing in a programmable fashion without sacrificing performance due to data fetch stalls when accessing large shared tables or external memory, leading to reduced throughput.
Innovation Solution
A match processing unit (MPU) is introduced to perform table-based actions in each stage of a network pipeline, combining with a table engine to extract fields, fetch results, and execute instructions deterministically, preventing data miss stalls and maintaining target packet processing rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If NPUs or CPUs are used to process packets in a programmable fashion, then adaptability and versatility are improved, but productivity deteriorates due to data fetch stalls from large shared tables or external memory
Solution Approach 1:
The patent segments the packet processing function into distinct components: a table engine dedicated to table lookups and data fetching, and match processing units (MPUs) dedicated to packet processing actions. This segmentation allows the table engine to handle memory access independently, preventing data fetch stalls from blocking the MPUs and maintaining high packet processing rates while preserving programmable capability.
Solution Approach 2:
The table engine acts as an intermediary between the MPUs and the large shared tables or external memory. It buffers table data in on-chip memory and handles all data fetching operations, serving as a mediator that eliminates the need for MPUs to directly access slow external memory, thereby preventing productivity deterioration while maintaining adaptability.
2Adaptability or versatility
If data is fetched from large shared tables or external memory during packet processing, then adaptability is improved, but loss of time increases due to processor stalls
Solution Approach 1:
The table engine performs preliminary actions by pre-fetching and buffering table data in on-chip memory before the MPUs need it for packet processing. This preliminary data preparation eliminates the need for processors to stall during runtime when accessing tables, as all required data is already available in fast on-chip memory.
Solution Approach 2:
The table engine serves as an intermediary that handles all time-consuming data fetching operations from external memory, preventing these operations from causing processor stalls. The MPUs interact only with the table engine through well-defined interfaces, ensuring that packet processing instructions execute without interruption from memory access delays.
3Quantity of substance
If multiple access requests are made to the same memory substructure, then data completeness is improved, but loss of time increases due to latency penalties
Solution Approach 1:
The table engine performs preliminary data loading from external memory into on-chip memory, organizing complete table data sets before they are needed for packet processing. This preliminary action ensures that all required data is available locally, eliminating the need for multiple time-consuming access requests to external memory substructures during packet processing.
Solution Approach 2:
The patent transitions from a single-dimensional memory access model (direct MPU access to external memory) to a two-dimensional hierarchy: fast on-chip memory for immediate access and slower external memory for bulk storage. The table engine manages this hierarchy, loading complete data sets into the faster on-chip dimension, thereby eliminating latency penalties from repeated external memory accesses.
Data Source
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AI summary
Methods and devices for processing packets with reduced data stalls are provided. The method comprises: (a) receiving a packet comprising a header portion and a payload portion, wherein the header portion is used to generate a packet header vector; (b) producing a table result by performing packet match operations, wherein the table result is generated based at least in part on the packet header vector and data stored in a match table; (c) receiving, at a match processing unit, the table result and an address of a set of instructions associated with the match table; and (d) performing, by the match processing unit, one or more actions in response to the set of instructions until completion of the instructions, wherein the one or more actions comprise modifying the header portion, updating memory based data structure or initiating an event.