Matched Buffer Decompression Circuit for Stall-Free Data Loading

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Solution Overview

Problem

Existing display devices face inefficiencies in data transmission due to pipeline stalls and increased decompression overhead, which can lead to decreased data compression ratios and increased energy consumption, particularly when transferring compressed data across large physical distances.

Innovation Solution

The implementation of a decompression circuit with matched buffers and clock signals that synchronize data loading to maintain a timing margin, allowing data to be loaded into data elements in a single internal clock cycle, thereby eliminating asynchronous delays and reducing the complexity of the decompression process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If data is transferred across large physical distances in display devices, then data transmission capability is improved, but pipeline stalls and decompression overhead increase

Engineering Contradiction:
Improvephysical distance for data transferVSAvoiddata transmission efficiency
Core Design Contradiction:
Length of moving objectVSProductivity

Solution Approach 1:

The decompression circuit is divided into multiple pipeline stages, with each stage handling a specific portion of the decompression process. This segmentation allows data to be processed in parallel across stages, reducing overall transmission time and eliminating pipeline stalls that would occur in a monolithic design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Compressed data is pre-loaded into buffers before the actual decompression process begins. This preliminary action ensures that data is ready and available when needed by subsequent pipeline stages, preventing stalls caused by data unavailability during transmission across physical distances.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If traditional decompression circuits are used, then data can be transferred, but decompression overhead increases and compression ratio decreases

Engineering Contradiction:
Improvedata transfer capabilityVSAvoiddata compression ratio
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The decompression circuit maintains continuous operation through overlapping pipeline stages, where each stage processes data continuously without idle periods. This continuity eliminates gaps in the decompression process, reducing overhead and maintaining high compression ratios by ensuring every clock cycle contributes to useful work.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

Buffers serve as intermediaries between the compressed data input and the decompression pipeline stages. These buffers decouple the data transmission from the decompression process, allowing optimal compression ratios to be achieved without compromising transfer capability, as the buffers manage the flow and timing independently.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If asynchronous delays are present in the decompression process, then data can be loaded, but timing margins are violated and bugs increase

Engineering Contradiction:
Improvedata loading flexibilityVSAvoidtiming margin compliance
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The decompression circuit uses synchronous clock signals to periodically advance data through each pipeline stage at predetermined intervals. This periodic action ensures that timing margins are consistently maintained across all stages, eliminating the unpredictable delays and bugs associated with asynchronous operations while preserving data loading capability.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20240087539A1Method and apparatus for matched buffer decompression
Publication Date: 2024.03.14 TEXAS INSTRUMENTS INC
  • US20240087539A1 patent drawing
  • US20240087539A1 patent drawing
  • US20240087539A1 patent drawing

AI summary

A circuit includes a first clock having a first clock output and a second clock having a second clock output. The circuit also includes a first buffer having a first buffer input, a second buffer input, and a first buffer output, the second buffer input coupled to the first clock output and a second buffer having a third buffer input, a fourth buffer input, and a second buffer output, the third buffer input coupled to the first buffer output and the fourth buffer input coupled to the second clock output. Additionally, the circuit includes a first element of data memory having a first data input and a first data output, the first data input coupled to the first buffer output and a second element of data memory having a second data input and a second data output, the second data input coupled to the second buffer output.