Multi-Level Modulator With Matched Encoding for Lower Latency
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Solution Overview
Problem
Existing communication modulators for high-speed applications like 40G/100G communication over copper cables or single-mode fiber suffer from high complexity and latency, making them unsuitable for efficient data transmission due to excessive redundancy and latency introduced by interleaving processes.
Innovation Solution
A multi-level modulator is introduced, featuring a symbol mapper and a multi-level encoder with an inner and outer encoder, where the information block size of the inner encoder matches the field size of the outer encoder, reducing complexity and latency by confining errors to symbol boundaries, thus omitting the need for interleaving and reducing hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional interleaving processes are used for error correction, then reliability is improved, but device complexity and latency increase
Solution Approach 1:
The patent extracts and removes the interleaving process from the communication system. By confining errors to symbol boundaries through the multi-level encoding structure, the patent eliminates the need for interleaving hardware, thereby reducing device complexity while maintaining error correction capability through the inner and outer encoder architecture.
2Reliability
If traditional interleaving processes are used for error correction, then reliability is improved, but latency increases
Solution Approach 1:
The patent removes the interleaving process that causes latency. By designing a multi-level encoder where the inner encoder's information block size matches the outer encoder's field size, errors are confined to symbol boundaries, eliminating the need for time-consuming interleaving operations and reducing transmission latency.
3Reliability
If redundancy is increased for error protection, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent applies partial encoding where only the information block from the inner encoder is encoded by the outer encoder, rather than encoding all data with maximum redundancy. This partial action approach provides sufficient error protection at symbol boundaries while avoiding excessive redundancy that would reduce data transmission efficiency and productivity.
4Device complexity
If multi-level encoding with matched block sizes is used, then device complexity is reduced, but error correction capability may be limited
Solution Approach 1:
The patent segments the encoding process into two distinct levels: an inner encoder that processes data blocks and an outer encoder that processes fields. This segmentation allows each encoder to operate independently with optimized parameters, reducing overall device complexity while maintaining robust error correction capability through the hierarchical structure.
Solution Approach 2:
The patent implements a nested encoding structure where the inner encoder's output becomes the outer encoder's input. The inner encoder's information block size is matched to the outer encoder's field size, creating a nested architecture that simplifies hardware implementation while providing multi-layer error protection, with the outer encoder correcting errors that the inner encoder cannot handle.
Data Source
AI summary
For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.