Matched Filter Bank for Low-Latency Sample Clock Phase Detection
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Solution Overview
Problem
Existing data processing systems face significant latency in determining the proper phase and frequency of a sampling clock, which is critical for accurate data sampling, due to complex calculations and noise presence in the system.
Innovation Solution
The implementation of a bank of matched filters and a logic circuit to determine the phase of the sampling clock by detecting patterns corresponding to different phases, allowing for reduced latency in clock phase determination through pattern recognition and noise filtering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If complex algorithms are used to perform zero phase start and determine clock phase quickly, then latency in determining sample clock phase is reduced, but the calculations become very complex and prone to error due to noise presence
Solution Approach 1:
The patent segments the timing pattern detection into multiple parallel matched filters, each tuned to detect the timing pattern at a different phase. Instead of using one complex algorithm to determine phase, the system divides the problem into simpler parallel operations where each filter independently checks for pattern presence at its specific phase, eliminating the need for complex sequential calculations.
Solution Approach 2:
The patent changes the parameter being measured from complex timing calculations to simple pattern presence detection. By transforming the problem into detecting whether a known timing pattern exists at different phases using matched filters, the system converts a complex phase determination problem into simpler binary detection tasks that are more robust to noise.
2Loss of time
If complex algorithms are used to determine clock phase, then latency is reduced, but accuracy decreases due to noise presence making calculations prone to error
Solution Approach 1:
The patent converts the harmful effect of noise on complex calculations into a beneficial approach by using simple pattern matching. Instead of trying to perform accurate complex calculations in the presence of noise, the system uses matched filters that simply detect the presence or absence of the timing pattern at different phases. This binary detection approach is inherently more robust to noise while still providing accurate phase determination.
3Measurement precision
If Viterbi detector output is used to determine sample clock phase, then phase determination is performed, but substantial latency is introduced that negatively impacts frequency determination
Solution Approach 1:
The patent performs preliminary action by detecting the timing pattern phase before the main data processing begins. The matched filters are applied to the raw received signal during a preamble or training sequence to establish the initial clock phase, eliminating the need to wait for Viterbi detector processing. This preliminary phase determination enables faster frequency adjustment and reduces overall system latency.
Data Source
AI summary
Various embodiments of the present invention provide systems and methods for phase identification in data processing systems. As one example, a circuit is disclosed that includes a bank of matched filters with two or more matched filters tuned to detect patterns corresponding to a timing pattern sampled using different phases of a sample clock. In particular, the bank of matched filters includes at least a first matched filter tuned to detect a first pattern corresponding to the timing pattern sampled using a first phase of a sample clock, and a second matched filter tuned to detect a second pattern corresponding to the timing pattern sampled using a second phase of the sample clock. The circuits further include a logic circuit operable to determine whether the sample clock is closer to the first phase or the second phase based on an output of the first matched filter and an output of the second matched filter.