Matched Filter Front End for Reduced-Rate Viterbi Decoding
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Solution Overview
Problem
Existing data decoding systems face challenges in increasing bandwidth without substantial power consumption and design complexity, particularly due to limitations in Viterbi decoder design and sample clock rate adjustments.
Innovation Solution
The implementation of a matched filter bank that processes a series of symbols at a reduced clock rate, using multiple matched filters to detect specific bit sequences and generate symbol proxies, which are then processed by a Viterbi detector operating at a lower frequency, thereby reducing the effective clock rate without increasing the complexity of the Viterbi decoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the sample clock rate is increased to increase bandwidth, then the bandwidth is improved, but the power consumption of the Viterbi decoder increases considerably
Solution Approach 1:
The system segments the data processing function into two stages: a matched filter bank that operates at the full sample clock rate to process high-bandwidth signals, and a Viterbi decoder that operates at a reduced clock rate. The matched filter bank prepares the data by detecting bit sequences and generating symbol proxies, which are then fed to the Viterbi decoder. This segmentation allows the power-hungry Viterbi decoder to operate at a lower frequency while the overall system maintains high bandwidth capability through the parallel matched filter bank.
2Speed
If the sample clock rate is increased to increase bandwidth, then the bandwidth is improved, but the Viterbi decoder design complexity increases
Solution Approach 1:
The system segments the data processing function into two stages: a matched filter bank that operates at the full sample clock rate to process high-bandwidth signals, and a Viterbi decoder that operates at a reduced clock rate. The matched filter bank prepares the data by detecting bit sequences and generating symbol proxies, which are then fed to the Viterbi decoder. This segmentation allows the power-hungry Viterbi decoder to operate at a lower frequency while the overall system maintains high bandwidth capability through the parallel matched filter bank.
Solution Approach 2:
The matched filter bank serves as an intermediary between the high-speed analog-to-digital converter and the Viterbi decoder. It processes the high-rate digital signal at the sample clock frequency, extracting bit sequence information and generating symbol proxies that represent the data at a reduced rate. This intermediary stage enables the Viterbi decoder to operate at a lower clock rate while still handling high-bandwidth input signals, thereby reducing the complexity of the decoder design.
3Speed
If parallel decoders are used to reduce effective clock rate, then the clock rate is reduced, but the logic size of the Viterbi trellis increases substantially
Solution Approach 1:
The matched filter bank serves as an intermediary between the high-speed analog-to-digital converter and the Viterbi decoder. It processes the high-rate digital signal at the sample clock frequency, extracting bit sequence information and generating symbol proxies that represent the data at a reduced rate. This intermediary stage enables the Viterbi decoder to operate at a lower clock rate while still handling high-bandwidth input signals, thereby reducing the complexity of the decoder design.
Data Source
AI summary
Various embodiments of the present invention provide systems and methods for reduced clock rate data processing. As an example, a circuit is disclosed that includes a matched filter bank that receives a series of symbols at a rate corresponding to a sample clock. The matched filter bank includes a first matched filter tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, and a second matched filter tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence. The circuit further includes a detector circuit that processes a series of symbol proxies including the first symbol proxy and the second symbol proxy at a rate corresponding to a reduced rate clock. The reduced rate clock is the sample clock divided by a factor.