Matching Layout Circuit With Integrated Dummy and Mismatch Marks
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Solution Overview
Problem
Conventional analog circuits consume significant area due to dummy marks, which are disadvantageous for circuit design and layout, especially when transistors requiring high current accuracy are placed away from the outermost transistors.
Innovation Solution
A matching layout circuit integrating a medium mismatch mark, a basic mismatch mark, and a dummy mark, where the dummy mark is repurposed as the basic mismatch mark, with transistors of the same size, arranged in a specific sequence to save area without affecting circuit characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dummy mark is placed surrounding transistors for protection, then current accuracy is improved, but area consumption increases significantly
Solution Approach 1:
The patent combines the dummy mark with the basic mismatch mark into a single integrated structure. The dummy mark is positioned at the outermost periphery while the basic mismatch mark is positioned inside it, forming a unified layout that serves both protection and mismatch compensation functions simultaneously, thereby reducing total area consumption while maintaining current accuracy.
Solution Approach 2:
The integrated mark structure performs multiple functions: the dummy mark provides protection against gradient effects and ensures current accuracy, while the basic mismatch mark compensates for process variations. By merging these two previously separate structures into one, the design achieves multi-functionality in a single layout element, reducing area while maintaining both protective and compensatory functions.
2Measurement precision
If transistors are placed away from outermost positions for high current accuracy, then measurement precision is improved, but area consumption increases
Solution Approach 1:
The patent merges the protective dummy mark with the functional basic mismatch mark, allowing transistors to be positioned optimally within the integrated structure. This combination enables high current accuracy transistors to be placed in the basic mismatch mark region while the dummy mark provides peripheral protection, achieving both accuracy and area efficiency.
3Reliability
If separate dummy mark and basic mismatch mark are used for protection and mismatch compensation, then reliability is improved, but area consumption increases
Solution Approach 1:
The patent integrates the dummy mark and basic mismatch mark into a single unified structure where the dummy mark is positioned at the outermost periphery and the basic mismatch mark is positioned inside it. This merged structure maintains both protective and mismatch compensation functions while significantly reducing the total area required compared to using separate structures.
Solution Approach 2:
The basic mismatch mark is nested within the dummy mark structure, forming a concentric arrangement where the inner basic mismatch mark benefits from the outer dummy mark's protective function. This nesting approach allows both structures to coexist in a compact configuration, maintaining reliability while minimizing area consumption.
Data Source
AI summary
A matching layout circuit includes a medium mismatch mark, a basic mismatch mark, and a dummy mark. The medium mismatch mark is disposed in a center of the matching layout circuit, and includes a plurality of first transistors. The first transistors are disposed in the medium mismatch mark, and configured to receive a first current. The basic mismatch mark is disposed outside the medium mismatch mark, and includes a plurality of second transistors. The second transistors are disposed in the basic mismatch mark, and configured to receive a second current. A first accuracy of the first current is higher than a second accuracy of the second current. The dummy mark is disposed outside the basic mismatch mark, and includes a plurality of third transistors. The third transistors are disposed in the dummy mark. The sizes of the first transistors, the second transistors, and the third transistors are the same.