Material Tester Filter Circuit for Rounding-Error-Free Averaging
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Solution Overview
Problem
Material testers face inaccuracies in data display due to rounding errors generated by digital filters during moving average calculations, which are not effectively addressed by increasing bit length or circuit size, leading to errors in integrated values.
Innovation Solution
A digital filter configuration with cascaded stages of 'n' data delay elements, an adder, a divider, and a remainder delay element that incorporates the remainder back into the adder, ensuring no rounding error is integrated, allowing for high-accuracy filtering without increasing circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a digital filter using a window function is employed, then noise removal capability is improved, but circuit size increases due to requiring multipliers and filter coefficient memory
Solution Approach 1:
The patent replaces expensive multipliers with simple adders and shift registers. The moving average filter uses n adders and n delay elements (flip-flops) to achieve noise removal without requiring complex multiplication operations, significantly reducing circuit complexity while maintaining filtering effectiveness
Solution Approach 2:
The patent changes the filtering approach from multiplication-based window functions to addition-based moving average calculation. By using n adders and delay elements to compute the average of n consecutive samples, the system achieves noise removal through parameter-based averaging rather than complex mathematical operations
2Device complexity
If rounding is used in the digital filter calculation, then circuit complexity is reduced, but measurement precision deteriorates due to rounding errors being integrated
Solution Approach 1:
The patent introduces a feedback mechanism where the remainder from the division operation is stored in a remainder delay element and fed back to the adder. This feedback ensures that rounding errors from integer division are compensated in subsequent calculations, preventing error accumulation while maintaining simple integer arithmetic throughout the filter
Solution Approach 2:
The patent compensates for potential rounding errors beforehand by incorporating the remainder feedback mechanism. By anticipating that integer division will produce rounding errors, the system pre-configures the feedback path to cancel these errors before they accumulate through the integration process
Data Source
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AI summary
In order to provide a material tester having a digital noise removal filter capable of high-accuracy filtering without generating an error caused by a rounding calculation using a simple configuration even when an integrated value obtained by inputting an averaged differential signal to an integrator (28) is displayed on a display unit (24), a filter circuit (60) is provided in which - "n" data delay elements (D1 ... Dn) are cascaded to sequentially accumulate input data from a sensor (40),- an adder (ADD) is configured to obtain a total sum of data output from each of the "n" delay elements, and- a divider (DIV) is configured tooutput a quotient obtained by dividing an output of the adder by the number "n" of the delay elements as averaged data andoutput a remainder to a remainder delay element (Dre).In each calculation, data output from each of the "n" delay elements and the remainder value output from the divider in the previous calculation are input to the adder, and an addition process for obtaining a total sum thereof is executed.