Material Tester Digital Filter for Rounding-Free Moving Averages
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Solution Overview
Problem
Material testers face inaccuracies in data display due to rounding errors generated by digital filters during moving average calculations, which are not effectively addressed by increasing bit length or circuit size, leading to reduced accuracy and larger circuit configurations.
Innovation Solution
A digital filter configuration with cascaded stages of 'n' data delay elements, an adder, a divider, and a remainder delay element that returns the remainder to the adder, ensuring the remainder's absolute value is ≤ '½' of 'n', allowing for accurate averaging without rounding errors and maintaining a simple circuit configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a digital filter using a window function is employed to remove noise from sensor data, then measurement precision is improved, but device complexity increases due to the need for filter coefficient memory and multipliers
Solution Approach 1:
The patent replaces complex multipliers with simple adders that perform repeated addition instead of multiplication. The filter coefficients are implemented as simple time delays (shifting operations) rather than stored values requiring memory. This substitution of complex operations with simpler, shorter-lived computational steps achieves the same noise filtering effect without requiring filter coefficient memory or multiplier circuits.
Solution Approach 2:
The patent substitutes the mathematical operation of multiplication (required by window function filters) with repeated addition operations. Instead of using multipliers to compute weighted sums with window function coefficients, the system uses adders to perform incremental additions over time periods, achieving equivalent filtering through a different computational mechanism that requires simpler hardware.
2Manufacturing precision
If the number of bits is increased to prevent rounding errors in the digital filter, then manufacturing precision is improved, but device complexity and circuit size increase
Solution Approach 1:
The patent maintains continuous accumulation of values in the adder without interruption or rounding. By continuously adding values over the time period and only performing the final division once the complete sum is obtained, the system avoids intermediate rounding errors that would occur with fixed-bit representations. This continuous computational approach preserves precision without requiring increased bit length throughout the circuit.
Solution Approach 2:
The patent performs the division operation only after all addition operations are complete, rather than dividing at each intermediate step. This preliminary completion of the accumulation phase before the final division ensures that no rounding errors are introduced during the calculation process, maintaining full precision throughout the computation without requiring additional bits.
3Measurement precision
If a digital filter is inserted between the linear encoder and integrator to remove noise, then measurement precision is improved, but rounding errors are integrated and amplified, worsening manufacturing precision
Solution Approach 1:
The patent introduces an intermediary computational structure where the adder accumulates all differential values before the final division by the integrator. This intermediary accumulation step acts as a buffer that preserves the full precision of the summed values, preventing rounding errors from being introduced at the filter stage and subsequently amplified by the integrator's accumulation function.
Data Source
AI summary
Data output from each of the “n” delay elements and a remainder value output from a divider in the previous calculation are input to an adder, and an addition process for obtaining a total sum thereof is executed. In addition, a division process is performed by dividing the total sum output from the adder by “n,” and a quotient and a remainder are output from the divider. The remainder is delayed by a remainder delay element by one clock, is output to the adder, and is added in the next calculation.