Material Testing Machine Signal Timing Compensation
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Solution Overview
Problem
In material testing machines, synchronizing synchronization signals across multiple devices with varying transmission line lengths and configurations is challenging, leading to difficulties in ensuring simultaneous signal arrival and requiring redesigns for device replacements with different pin arrangements, which complicates space efficiency and compatibility.
Innovation Solution
The implementation of synchronization signal distribution adjustment circuits in the master unit, which measure time differences and adjust signal delays to synchronize signals across slave units, ensuring simultaneous signal arrival despite varying wiring lengths and configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If equal-length wirings (meander wiring) are used for all signal wirings, then synchronization signal arrival timing is unified, but signal quality deteriorates and device space increases
Solution Approach 1:
The patent applies local quality by making each synchronization signal wiring have different characteristics (length, routing) optimized for its specific path, rather than forcing all wirings to be equal length. This allows each signal path to maintain optimal signal quality while still achieving synchronization through compensating for the individual path differences.
Solution Approach 2:
The patent changes the parameter of wiring length from being uniform (equal-length wirings) to being variable (different lengths for different paths). By allowing wiring lengths to differ and compensating through timing adjustment, the patent avoids the signal quality deterioration that occurs when all wirings are forced to match the longest path.
2Manufacturing precision
If equal-length wirings are used for all signal wirings, then synchronization signal arrival timing is unified, but device space increases
Solution Approach 1:
The patent allows each wiring path to have its own optimal length and routing rather than forcing uniform equal-length wirings. This eliminates the need for space-consuming meander patterns and allows the PCB layout to be more compact, reducing overall device space while maintaining synchronization through individual path timing compensation.
3Adaptability or versatility
If device replacement with different pin arrangements is performed, then device compatibility increases, but transmission path redesign is required
Solution Approach 1:
The patent creates a universal synchronization signal distribution system that can accommodate different device pin arrangements without requiring transmission path redesign. The master unit generates and distributes synchronization signals to multiple slave units through a standardized interface, allowing devices from different manufacturers with different pinouts to be integrated without modifying the transmission path configuration.
Solution Approach 2:
The master unit acts as an intermediary that mediates between devices with different pin arrangements. It receives synchronization requirements from various slave units and distributes appropriately timed signals to each, translating between different device interfaces and maintaining system-wide synchronization without requiring redesign of individual transmission paths.
4Adaptability or versatility
If synchronization signal transmission paths have varying lengths and buffer configurations, then device connectivity flexibility increases, but signal arrival timing varies
Solution Approach 1:
The patent implements a feedback mechanism where the master unit measures the actual arrival time of synchronization signals at each slave unit and adjusts the transmission timing accordingly. This closed-loop approach allows the system to accommodate varying path lengths and buffer configurations while maintaining precise signal arrival timing, as the master unit compensates for each path's specific characteristics.
Data Source
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AI summary
A master unit (40) includes a synchronization signal source (41) that generates a synchronization signal and a synchronization signal distribution adjustment circuit (42) that adjusts a distribution timing of the synchronization signal to each of slave units (A) and (B). The synchronization signal distribution adjustment circuit (42) includes a period measurement circuit (43) that measures a period Ts of the synchronization signal output from the synchronization signal source (41), a time difference measurement circuit (44) that measures a time difference Td between a time point of the synchronization signal issued from the master unit (40) to the slave units (A) and (B) and a time point of the synchronization signal returned from the slave units (A) and (B) to the master unit (40), and a delay circuit (45) that delays the issuing time point of the synchronization signal to be transmitted from the master unit (40) to the slave units (A) and (B) based on the period Ts of the synchronization signal and the time difference Td.