Material Testing Synchronization Circuit for Unequal Signal Paths
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Solution Overview
Problem
In material testing machines, synchronizing synchronization signals across multiple devices is challenging due to varying transmission line lengths and different pin arrangements, leading to difficulties in ensuring simultaneous signal arrival and requiring redesigns for device replacement.
Innovation Solution
A control device with a master unit and slave units, where each slave unit has a synchronization signal distribution adjustment circuit that measures signal periods and time differences to adjust the signal delay, ensuring synchronized signal arrival across devices with different wiring configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If equal-length wirings (meander wiring) are used for all signal wirings, then synchronization signal arrival timing is improved, but wiring space requirement increases and signal quality deteriorates
Solution Approach 1:
The patent applies local quality by adjusting the delay time of the synchronization signal to each slave unit individually based on their specific transmission path characteristics. Instead of forcing all wirings to be equal length, each slave unit receives a customized delay adjustment that compensates for its specific path length and number of issuing/receiving elements, achieving synchronization without requiring uniform wiring lengths across all devices.
2Manufacturing precision
If equal-length wirings are used for all signal wirings, then synchronization signal arrival timing is improved, but signal quality deteriorates
Solution Approach 1:
The patent adjusts the delay time locally for each slave unit based on its specific transmission path characteristics rather than forcing uniform wiring lengths. This allows each slave unit to receive the synchronization signal with an optimized delay that maintains signal quality while achieving synchronization, avoiding the signal quality deterioration that would result from forcing all wirings to equal length.
3Adaptability or versatility
If device replacement with different pin arrangements is performed, then device adaptability is improved, but transmission path redesign is required
Solution Approach 1:
The patent changes the parameter of delay time dynamically based on the transmission path characteristics. When devices are replaced or reconfigured, the system measures the actual transmission path length and number of issuing/receiving elements, then adjusts the delay time parameter accordingly. This allows device replacement with different pin arrangements without requiring transmission path redesign, as the delay time parameter automatically adapts to the new configuration.
4Adaptability or versatility
If synchronization signal transmission path includes multiple branches and buffers, then device connectivity is improved, but synchronization signal arrival timing becomes difficult to control
Solution Approach 1:
The patent employs feedback by measuring the actual transmission path characteristics (length and number of issuing/receiving elements) for each slave unit and using this measured information to adjust the delay time. This feedback mechanism allows the system to accommodate complex transmission paths with multiple branches and buffers while maintaining precise synchronization, as the delay time is optimized based on the actual path characteristics rather than theoretical estimates.
Data Source
AI summary
A master unit includes a synchronization signal source that generates a synchronization signal and a synchronization signal distribution adjustment circuit that adjusts a distribution timing of the synchronization signal to each of slave units. The synchronization signal distribution adjustment circuit includes a period measurement circuit that measures a period of the synchronization signal output from the synchronization signal source, a time difference measurement circuit that measures a time difference between a time point of the synchronization signal issued from the master unit to the slave units and a time point of the synchronization signal returned from the slave units to the master unit, and a delay circuit that delays the issuing time point of the synchronization signal to be transmitted from the master unit to the slave units based on the period of the synchronization signal and the time difference.