Configurable Math Accelerator Configuration via Translation Controller
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Solution Overview
Problem
Existing microprocessor circuits face computational and power overhead due to continuous updates of configuration registers in math hardware accelerators, limiting flexibility and efficiency in signal processing applications.
Innovation Solution
A configuration controller that fetches, translates, and writes configuration data directly to math hardware accelerators via a data memory bus, offloading the microprocessor core and reducing repetitive operations, while maintaining flexibility for tailored signal processing functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If math hardware accelerators are interfaced via memory mapping to a microprocessor core, then flexibility and accessibility are improved, but computational overhead and power consumption increase due to continuous updates of configuration registers
Solution Approach 1:
A configuration controller is introduced as an intermediary component between the microprocessor core and the math hardware accelerators. The configuration controller handles all configuration register updates and translations, while the microprocessor core only needs to write once to a configuration memory location. This mediator eliminates the need for continuous microprocessor intervention, thereby reducing power consumption while maintaining system flexibility.
Solution Approach 2:
Configuration data is prepared and stored in a predetermined address space of the data memory in advance, structured according to specific data structure specifications. The configuration controller fetches and translates this pre-prepared configuration data before the math hardware accelerator needs to operate, eliminating the need for real-time configuration updates during operation and reducing ongoing power consumption.
2Adaptability or versatility
If math hardware accelerators are configured with numerous programmable parameters and configuration registers, then adaptability to specific applications is improved, but computational overhead increases due to continuous updates required
Solution Approach 1:
The configuration controller serves as an intermediary that manages all interactions with the numerous configuration registers. It translates a single high-level configuration write from the microprocessor into multiple low-level register updates, and handles all subsequent configuration changes without involving the microprocessor core. This eliminates computational overhead while preserving full adaptability through the numerous programmable parameters.
Solution Approach 2:
Configuration data is structured in a predetermined address space with specific data structure specifications that encode all necessary programmable parameters. This preliminary structuring allows the configuration controller to efficiently manage all configuration registers through a single initial configuration operation, eliminating repetitive computational overhead while maintaining adaptability.
3Productivity
If configuration data is translated and written to math hardware accelerators via a configuration controller, then computational burden on the microprocessor core is reduced, but system complexity increases
Solution Approach 1:
While the configuration controller adds a component to the system, it consolidates multiple configuration functions into a single dedicated unit. This intermediary handles translation, fetching, and register writing operations that would otherwise burden the microprocessor core. The net effect is reduced overall system complexity in terms of control logic distributed across the microprocessor, while improving computational efficiency.
4Adaptability or versatility
If the microprocessor core continuously updates configuration registers of math hardware accelerators, then real-time reconfiguration capability is improved, but power overhead and computational load increase
Solution Approach 1:
The configuration controller acts as an energy-efficient intermediary that handles all configuration register updates. When reconfiguration is needed, the microprocessor core simply writes new configuration data to a predetermined memory address, and the configuration controller autonomously handles the translation and distribution to relevant hardware accelerators. This maintains real-time reconfiguration capability while dramatically reducing the power overhead associated with continuous microprocessor involvement.
Solution Approach 2:
The system prepares configuration data in advance in a structured format in memory. When reconfiguration is required, this pre-structured data can be quickly fetched and translated by the configuration controller without requiring the microprocessor core to engage in lengthy update sequences, thereby enabling fast reconfiguration with minimal power consumption.
Data Source
AI summary
A microprocessor circuit may include a software programmable microprocessor core and a data memory accessible via a data memory bus. The data memory may include sets of configuration data structured according to respective predetermined data structure specifications for configurable math hardware accelerators, and sets of input data for configurable math hardware accelerators, each configured to apply a predetermined signal processing function to the set of input data according to received configuration data. A configuration controller is coupled to the data memory via the data memory bus and to the configurable math hardware accelerators. The configuration controller may fetch the configuration data for each math hardware accelerator from the data memory and translate the configuration data. The configuration controller may transmit each set of configuration data to the corresponding configurable math hardware accelerator and write the configuration data to configuration registers of the math hardware accelerator.