Matrix Cache Structure with Split Read-Only and Read-Write Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing cache structures for processors face high hardware cost, complexity, and power consumption due to the large size of matrices, especially in matrix computation, as they require read-write permissions across multiple levels, leading to increased delay and interference between read-only and read-write data.
Innovation Solution
A cache structure with N levels of caches, where each level-i cache node includes a read-only and read-write region, with higher levels sharing cache nodes, optimizing for matrix computation by separating read-only and read-write operations, reducing hardware cost and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a unified read-write cache structure is used for matrix computation, then the cache can store both input and output matrices, but the hardware cost, complexity, and power consumption increase significantly
Solution Approach 1:
The cache is segmented into separate read-only cache regions and read-write cache regions at each level. The read-only cache stores input matrices while the read-write cache stores output matrices, eliminating the need for unified read-write permissions across the entire cache structure. This segmentation reduces complexity while maintaining full storage capability for both input and output matrices.
Solution Approach 2:
Different regions of the cache are assigned different permission qualities: read-only regions for input matrix storage and read-write regions for output matrix storage. This local differentiation of cache region properties optimizes the structure for matrix computation workloads while reducing overall hardware complexity and power consumption.
2Adaptability or versatility
If read-write permissions are provided across all cache levels for matrix computation, then output matrices can be stored, but interference between read-only and read-write operations increases delay
Solution Approach 1:
The cache is divided into separate read-only and read-write paths at each level. The read-only cache path handles input matrix access while the read-write cache path handles output matrix access, preventing interference between read and write operations. This segmentation eliminates the delay caused by read-write permission conflicts while maintaining full write capability for output matrices.
3Use of energy by stationary object
If the cache structure is optimized for matrix computation with separated read-only and read-write regions, then hardware overhead and power consumption are reduced, but the cache structure becomes more specialized
Solution Approach 1:
The cache structure applies local quality optimization by assigning read-only permissions to regions storing input matrices and read-write permissions to regions storing output matrices. This targeted permission assignment reduces power consumption for regions that don't require write operations, while maintaining the necessary write capability for output matrices. The structure remains adaptable to matrix computation workloads while being more specialized for this specific application.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A cache structure and an electronic device. The cache structure comprises an N-level cache, an ith-level cache in the N-level cache comprises at least one i-level cache node, and each i-level cache node comprises an i-level read-only cache region with a read-only permission and an i-level read-write cache region with a read-write permission. Each plurality of i-level cache nodes share one (i+1)-level cache node. An Nth-level cache is electrically connected to an external memory, and each level-1 cache node is electrically connected to a corresponding computing unit. The read-only cache region in the N-level cache is configured to cache an input matrix as a computing input parameter in matrix computing, and to transmit the input matrix between the external memory and a plurality of computing units. The read-write cache region in the N-level cache is configured to cache an output matrix as a computing output parameter in matrix computing, and to transmit the output matrix between the external memory and the plurality of computing units.