Matrix Multiplication Circuit With Multi-Precision Partial Sums
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Solution Overview
Problem
Existing neural network computations face challenges in performing matrix multiplications with high precision and reduced overflow, particularly when using floating point formats with limited bit widths, leading to precision loss and overflow issues.
Innovation Solution
A special-purpose hardware circuit is designed to perform matrix multiplications with enhanced precision by converting input activation and weight values to higher precision formats, generating product values with increased dynamic range, and combining these values to minimize overflow and precision loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If floating point formats with limited bit widths are used for matrix multiplication, then device complexity is reduced, but manufacturing precision deteriorates due to precision loss and overflow issues
Solution Approach 1:
The patent transitions from a single-precision computational approach to a multi-precision architecture by introducing separate first precision and second precision computational paths. This dimensional expansion allows the system to simultaneously maintain low-complexity operations for common cases while providing high-precision computation when needed, effectively resolving the contradiction between bit width and computation precision.
Solution Approach 2:
The system dynamically changes precision parameters based on computational needs by selecting between first precision and second precision modes. The precision selection mechanism allows the computational precision parameter to be adjusted without changing the fundamental hardware architecture, enabling the system to adapt between low-complexity and high-precision operations as required by different computational tasks.
2Manufacturing precision
If higher precision formats are used for product values, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the computational architecture into distinct first precision and second precision computational paths, each optimized for specific precision requirements. This segmentation allows the system to allocate higher precision resources only where needed in the computational workflow, rather than requiring all components to operate at maximum precision, thereby improving product value precision while controlling overall device complexity.
Solution Approach 2:
The hardware circuit is designed with multi-functional capability to perform both first precision and second precision computations using the same physical infrastructure. The computational units can operate in different precision modes depending on the computational requirements, making the hardware universally applicable to both low-complexity and high-precision tasks without requiring separate dedicated circuits for each precision level.
Data Source
AI summary
Methods, systems, and apparatus for performing a matrix multiplication using a hardware circuit are described. An example method begins by obtaining an input activation value and a weight input value in a first floating point format. The input activation value and the weight input value are multiplied to generate a product value in a second floating point format that has higher precision than the first floating point format. A partial sum value is obtained in a third floating point format that has a higher precision than the first floating point format. The partial sum value and the product value are combined to generate an updated partial sum value that has the third floating point format.