Matrix Compression Accelerator for Faster DRAM-SRAM Transfers
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Solution Overview
Problem
The existing technologies face inefficiencies in transferring large matrices between data memories with different access times, particularly between slower external dynamic random access memory (DRAM) and faster local static random access memory (SRAM), which hampers the processing speed of convolutional neural networks (CNNs) due to memory alignment and transfer length restrictions.
Innovation Solution
A matrix compression accelerator (MCA) system that implements lossless data compression and decompression using a multi-stage process, including 2D-to-1D transformation and 1D-to-2D transformation, facilitated by a direct memory access (DMA) controller, to optimize data transfers between external and local data memories, thereby reducing the number of memory accesses and enhancing processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred directly between external DRAM and local SRAM without compression, then transfer simplicity is maintained, but transfer time increases due to the slower access time of external memory
Solution Approach 1:
The patent segments the data transfer process into multiple stages: compression stage, transfer stage, and decompression stage. By dividing the transfer of large matrices into smaller compressed blocks, the system can efficiently utilize the slower external memory while maintaining high-speed processing through parallel operations and reduced transfer volumes.
Solution Approach 2:
The patent applies preliminary compression to data before transfer from external DRAM to local SRAM. This preliminary action reduces the volume of data that needs to be transferred, thereby reducing the time spent on memory access operations and improving overall transfer speed.
2Productivity
If compression and decompression operations are performed, then data transfer volume is reduced and transfer speed is improved, but processing complexity increases
Solution Approach 1:
The patent introduces a compression accelerator as an intermediary component between external DRAM and local SRAM. This dedicated hardware component handles the complex compression and decompression operations, isolating the complexity from the main system while providing efficient data transfer capabilities.
Solution Approach 2:
The compression accelerator operates autonomously to perform compression and decompression operations without requiring extensive intervention from the main processing system. This self-service capability reduces the overall system complexity while maintaining high transfer efficiency.
3Reliability
If more memory resources are allocated for uncompressed data storage, then data availability for computation is improved, but memory resource consumption increases
Solution Approach 1:
The patent changes the state of data by applying compression algorithms that reduce the volume of data stored in memory. By transforming data from uncompressed to compressed form, the system maintains data availability for computation while significantly reducing memory resource consumption.
Data Source
AI summary
A matrix compression/decompression accelerator (MCA) system/method that coordinates lossless data compression (LDC) and lossless data decompression (LDD) transfers between an external data memory (EDM) and a local data memory (LDM) is disclosed. The system implements LDC using a 2D-to-1D transformation of 2D uncompressed data blocks (2DU) within LDM to generate 1D uncompressed data blocks (1DU). The 1DU is then compressed to generate a 1D compressed superblock (CSB) in LDM. This LDM CSB may then be written to EDM with a reduced number of EDM bus cycles. The system implements LDD using decompression of CSB data retrieved from EDM to generate a 1D decompressed data block (1DD) in LDM. A 1D-to-2D transformation is then applied to the LDM 1DD to generate a 2D decompressed data block (2DD) in LDM. This 2DD may then be operated on by a matrix compute engine (MCE) using a variety of function operators.