Matrix DAC Layout With Selective DEM for Lower Hardware Overhead
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Solution Overview
Problem
Conventional digital-to-analog converters (DACs) face challenges in reducing hardware size while maintaining high resolution and speed, particularly due to the exponential increase in hardware complexity and power consumption associated with traditional dynamic element matching methods.
Innovation Solution
The proposed DAC employs a dynamic element matching technique where only the upper bits randomize the arrangement of unit cells, reducing hardware size by eliminating the need for randomization of lower bits, and arranges unit cells in a matrix formation to selectively choose rows and columns based on input bits, thereby optimizing hardware usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional dynamic element matching methods are used to improve mismatch between unit cells, then measurement precision is improved, but device complexity increases exponentially
Solution Approach 1:
The patent divides the N-bit digital input signal into two separate parts: upper M bits and lower (N-M) bits. The upper bits are processed through the DEM unit with randomization, while the lower bits are processed separately without randomization. This segmentation allows the system to achieve mismatch reduction for the significant upper bits while avoiding the exponential complexity growth that would occur if all N bits were randomized.
Solution Approach 2:
The patent applies dynamic element matching randomization selectively only to the upper M bits that have greater impact on measurement precision, rather than uniformly applying it to all N bits. This local application of quality control optimizes the mismatch reduction where it matters most while minimizing the hardware complexity overhead.
2Measurement precision
If traditional dynamic element matching methods are used to improve mismatch between unit cells, then measurement precision is improved, but power consumption increases
Solution Approach 1:
By segmenting the input bits and applying DEM randomization only to the upper M bits rather than all N bits, the patent reduces the number of randomization operations required. This directly reduces power consumption while maintaining measurement precision for the most significant bits.
Solution Approach 2:
The patent applies partial randomization only to the extent necessary (upper M bits) rather than excessive randomization of all bits. This partial action is sufficient to achieve the required measurement precision while minimizing power consumption.
3Measurement precision
If traditional dynamic element matching methods are used to improve mismatch between unit cells, then measurement precision is improved, but hardware size increases
Solution Approach 1:
The patent segments the bit processing into two separate paths: one for upper M bits that requires DEM randomization hardware, and another for lower (N-M) bits that uses simpler processing. This segmentation reduces the overall hardware size by eliminating the need for randomization hardware for the lower bits.
Solution Approach 2:
The patent introduces a dimensional separation in the processing architecture by treating upper and lower bits differently, with the upper bits going through the DEM randomization dimension and lower bits through a direct processing dimension. This dimensional change optimizes hardware utilization.
Data Source
AI summary
A digital-to-analog converter (DAC) includes a current array having a plurality of unit cells in a plurality of rows and a plurality of columns, an arbitrary switch box and processing circuitry configured to randomly select a subset of rows among the plurality of rows based on a plurality of first row selection signals, the subset of rows including first unit cells among the plurality of unit cells, randomly select one row among the plurality of rows based on a plurality of second row selection signals, select a subset of columns among the plurality of columns based on column selection signals, second unit cells among the plurality of unit cells being included in both the one row and the subset of columns, and generate an analog output signal corresponding to a digital input signal based on the first unit cells and the second unit cells.